公开(公告)号：US20060264036A1

公开(公告)日：2006-11-23

申请号：US11491816

申请日：2006-07-24

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

摘要翻译： 在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。 在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

公开(公告)号：US20050127514A1

公开(公告)日：2005-06-16

申请号：US10731377

申请日：2003-12-08

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Timothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Timothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

摘要翻译： 在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。 在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

公开(公告)号：US07084479B2

公开(公告)日：2006-08-01

申请号：US10731377

申请日：2003-12-08

申请人： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

发明人： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

IPC分类号： H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

公开(公告)号：US20060012014A1

公开(公告)日：2006-01-19

申请号：US10891605

申请日：2004-07-15

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Michael Lane ,  Qinghuang Lin ,  Robert Rosenberg ,  Thomas Shaw ,  Terry Spooner

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Michael Lane ,  Qinghuang Lin ,  Robert Rosenberg ,  Thomas Shaw ,  Terry Spooner

IPC分类号： H01L21/44

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832

摘要： The present invention provides a plastically and/or viscoelastically deformable layer that can be used in conjunction with a low-k dielectric (k of less than 4.0) to provide an electronic semiconductor structure having improved reliability. The deformable layer can be incorporated into various points within an electronic structure to dissipate energy within the structure that may cause the low-k dielectric material to crack or delaminate therefrom. Moreover, the presence of the deformable layer with the electronic structure improves the overall strength of the resultant structure.

摘要翻译： 本发明提供了可以与低k电介质（k小于4.0）结合使用的塑性和/或粘弹性变形层，以提供具有改进的可靠性的电子半导体结构。 可变形层可以结合到电子结构内的各个点中以消散结构内的能量，这可能导致低k电介质材料从其中破裂或分层。 此外，具有电子结构的可变形层的存在提高了所得结构的总体强度。

公开(公告)号：US07064064B2

公开(公告)日：2006-06-20

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US20050158985A1

公开(公告)日：2005-07-21

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy Dalton ,  Kenneth Davis ,  Chao-Kun Hu ,  Fen Jamin ,  Steffen Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael Lofaro ,  Sandra Malhotra ,  Chandrasekhar Narayan ,  David Rath ,  Judith Rubino ,  Katherine Saenger ,  Andrew Simon ,  Sean Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy Dalton ,  Kenneth Davis ,  Chao-Kun Hu ,  Fen Jamin ,  Steffen Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael Lofaro ,  Sandra Malhotra ,  Chandrasekhar Narayan ,  David Rath ,  Judith Rubino ,  Katherine Saenger ,  Andrew Simon ,  Sean Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US06975032B2

公开(公告)日：2005-12-13

申请号：US10319967

申请日：2002-12-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

公开(公告)号：US20060128163A1

公开(公告)日：2006-06-15

申请号：US10905065

申请日：2004-12-14

申请人： Shyng-Tsong Chen ,  Kaushik Kumar ,  Kelly Malone

发明人： Shyng-Tsong Chen ,  Kaushik Kumar ,  Kelly Malone

IPC分类号： H01L21/469

CPC分类号： H01L21/76802 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/76831

摘要： Damaged porous OSG layers and other damage may be chemically healed. Chemical healing is particularly advantageous in a porous OSG layer in a sub 90 nm ILD. For example, chemical healing may be by reacting the damage with an adhesion promoter having a “k” value comparable to the “k” value desired in the damaged material. Damaged porous OSG layers (which are hydrophilic) may be manipulated to prevent them from allowing moisture to reach copper lines. Undesirable copper out-diffusion can be controlled in ILDs having porous OSG geometry.

摘要翻译： 受损的多孔OSG层和其他损伤可以化学愈合。 在90nm以下的ILD中，化学愈合特别有利于多孔OSG层。 例如，化学愈合可以通过使损伤与具有与损伤材料中所需的“k”值相当的“k”值的粘合促进剂反应。 可以操纵损坏的多孔OSG层（其是亲水的）以防止它们使水分达到铜线。 可以在具有多孔OSG几何形状的ILD中控制不希望的铜外扩散。

公开(公告)号：US20100314767A1

公开(公告)日：2010-12-16

申请号：US12485366

申请日：2009-06-16

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/4846 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

摘要翻译： 提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案） 其中。 具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。 第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。 导电材料填充至少一个第一互连图案和至少一个第二互连图案。 还提供了形成这种自对准互连结构的方法。

公开(公告)号：US08415248B2

公开(公告)日：2013-04-09

申请号：US13474349

申请日：2012-05-17

申请人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

发明人： Shyng-Tsong Chen ,  Qinghuang Lin ,  Sampath Purushothaman ,  Terry A. Spooner ,  Shawn M. Walsh

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/4846 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L23/49894 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.

摘要翻译： 提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案） 其中。 具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。 第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。 导电材料填充至少一个第一互连图案和至少一个第二互连图案。 还提供了形成这种自对准互连结构的方法。