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109 条记录 (耗时 0.043 秒)

    Capacitor supported precharging of memory digit lines
    41.
    发明授权
    Capacitor supported precharging of memory digit lines 有权
    电容器支持对存储器数字线进行预充电

    公开(公告)号：US07423923B2

    公开(公告)日：2008-09-09

    申请号：US11642810

    申请日：2006-12-19

    申请人： Shigeki Tomishima

    发明人： Shigeki Tomishima

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： Circuits and methods are provided for precharging pairs of many digit lines. The final precharge voltage of the digit lines is different from the average of the digit line voltages prior to precharging. The final precharge voltage can be set by appropriately selecting the size of a capacitor in the precharge circuit.

    摘要翻译： 提供电路和方法用于对存储器数字线对进行预充电。 数字线的最终预充电电压与预充电之前的数字线电压的平均值不同。 可以通过适当选择预充电电路中的电容器的尺寸来设定最终预充电电压。

    Semiconductor memory device
    42.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06953960B2

    公开(公告)日：2005-10-11

    申请号：US09996574

    申请日：2001-11-30

    申请人： Shigeki Tomishima

    发明人： Shigeki Tomishima

    IPC分类号： G11C11/407 ,  G11C5/06 ,  G11C8/14 ,  G11C11/401 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/788 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10891 ,  G11C5/063 ,  G11C8/14 ,  G11C11/408 ,  H01L27/10897

    摘要： A first level metal interconnection line in a layer below a third level metal interconnection line serving as a main word line MWL is used as a shunting interconnection line and electrically connected to a first level polysilicon interconnection line constituting a sub word line SWL at prescribed intervals. By applying a hierarchical word line structure and a word line shunting structure both, a word line is driven into a selected state at high speed without increasing an array occupancy area and manufacturing steps.

    摘要翻译： 在作为主字线MWL的第三级金属互连线下方的层中的第一级金属互连线用作分流互连线，并且以规定的间隔电连接到构成子字线SWL的第一级多晶硅互连线。 通过应用分层字线结构和字线分流结构，字线被高速驱动到选定状态，而不增加阵列占用面积和制造步骤。

    Semiconductor device suitable for system in package
    43.
    发明申请
    Semiconductor device suitable for system in package 失效
    适用于封装系统的半导体器件

    公开(公告)号：US20050041482A1

    公开(公告)日：2005-02-24

    申请号：US10961146

    申请日：2004-10-12

    申请人： Shigeki Tomishima

    发明人： Shigeki Tomishima

    IPC分类号： G01R31/317 ,  G01R31/3185 ,  G11C5/00

    CPC分类号： G11C29/1201 ,  G01R31/31723 ,  G01R31/3185 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49171 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： In each of output buffer circuits arranged corresponding to respective output pads, a first output buffer having small current driving capability for a normal operation mode and a second output buffer having large current driving capability for a test operation mode are arranged in parallel with each other. One of the first and second output buffers is enabled and the other is set to an output high impedance state alternatively in accordance with a mode designating signal. Thus, an output buffer circuit capable of driving an output pad with optimal driving capabilities in a normal operation mode and in a test operation mode in a semiconductor device for use in a system in package is implemented.

    摘要翻译： 在对应于各个输出焊盘布置的每个输出缓冲器电路中，具有用于正常操作模式的小电流驱动能力的第一输出缓冲器和具有用于测试操作模式的大电流驱动能力的第二输出缓冲器彼此并联布置。 第一和第二输出缓冲器中的一个被使能，另一个根据模式指定信号交替地设置为输出高阻抗状态。 因此，实现了能够在正常操作模式和在用于封装系统的半导体器件中的测试操作模式下驱动具有最佳驱动能力的输出缓冲电路。

    Dynamic semiconductor memory device having excellent charge retention characteristics
    45.
    发明授权
    Dynamic semiconductor memory device having excellent charge retention characteristics 有权
    具有优异的电荷保持特性的动态半导体存储器件

    公开(公告)号：US06377508B1

    公开(公告)日：2002-04-23

    申请号：US09467916

    申请日：1999-12-21

    申请人： Shigeki Tomishima ,  Kazutami Arimoto

    发明人： Shigeki Tomishima ,  Kazutami Arimoto

    IPC分类号： G11C800

    CPC分类号： H03K3/356113 ,  G11C11/407 ,  G11C11/4085 ,  G11C11/4087

    摘要： Level converter converts a word line group specifying signal, which is sent from a row decoder and has amplitude of a power supply potential Vcc and a ground potential GND, into mutually complementary logic signals WD and ZWD of a high voltage Vpp and a negative potential Vbb. An RX decoder decodes an address signal to output a signal of an amplitude of (Vpp−Vbb) specifying a word line in a word line group. A word driver provided corresponding to each word line transmits a word line specifying signal or a negative potential to the corresponding word line in accordance with signals WD and ZWD sent from a level converting circuit. The nonselected word line receives negative potential Vbb from a word driver. The selected word line receives high voltage Vpp from the word driver. It is possible to suppress a channel leak current at a memory transistor in the nonselected memory cell, which may be caused by the potential change of the word line and/or bit line, and a charge holding characteristic of the memory cell can be improved.

    摘要翻译： 电平转换器将从行解码器发送并具有电源电位Vcc和接地电位GND的幅度的字线组指定信号转换成高电压Vpp和负电位Vbb的互补逻辑信号WD和ZWD 。 RX解码器解码地址信号，以输出指定字线组中的字线的（Vpp-Vbb）幅度的信号。 根据从电平转换电路发送的信号WD和ZWD，对应于每个字线提供的字驱动器将字线指定信号或负电位发送到对应的字线。 非选择字线从字驱动器接收负电位Vbb。 所选字线从字驱动器接收高压Vpp。 可以抑制可能由字线和/或位线的电位变化引起的非选择存储单元中的存储晶体管的沟道泄漏电流，并且可以提高存储单元的电荷保持特性。

    Signal potential conversion circuit
    46.
    发明授权
    Signal potential conversion circuit 有权

    公开(公告)号：US06373315B1

    公开(公告)日：2002-04-16

    申请号：US09793997

    申请日：2001-02-28

    申请人： Takaharu Tsuji ,  Shigeki Tomishima ,  Tsukasa Ooishi

    发明人： Takaharu Tsuji ,  Shigeki Tomishima ,  Tsukasa Ooishi

    IPC分类号： H03L500

    摘要： In a signal potential conversion circuit of a DRAM, a first P channel MOS transistor for charging a first node is connected in parallel with a second P channel MOS transistor and the second P channel MOS transistor is turned on in a pulse manner in response to a rising edge of an input signal. Further, the first P channel MOS transistor has its current drive ability defined to be approximately one-tenth of that of an N channel MOS transistor for discharging the first node. Accordingly, each of the first node and a second node can be charged and discharged quickly to enable conversion of a signal potential to be accomplished speedily.

    Synchronous type semiconductor memory device permitting reduction in ratio of area occupied by control circuit in chip area
    47.
    发明授权
    Synchronous type semiconductor memory device permitting reduction in ratio of area occupied by control circuit in chip area 失效
    同步型半导体存储器件允许减少芯片面积中控制电路占用的面积比

    公开(公告)号：US06301187B1

    公开(公告)日：2001-10-09

    申请号：US09226064

    申请日：1999-01-06

    申请人： Tsukasa Ooishi ,  Shigeki Tomishima

    发明人： Tsukasa Ooishi ,  Shigeki Tomishima

    IPC分类号： G11C800

    CPC分类号： G11C5/14 ,  G11C5/025 ,  G11C7/1072 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

    摘要： An address signal is transmitted to each bank by a common address bus. A column pre-decoder, and a row pre-decoder detect a selection of a corresponding bank in response to a signal transmitted by the address bus, and receive an address signal in response to a command signal from a command data bus. Circuits closer to the side of the address data bus and command data bus than to the circuit which latches the received data have a hierarchical power supply configuration.

    摘要翻译： 通过公共地址总线将地址信号发送到每个存储体。 列预解码器和行预解码器响应于地址总线发送的信号检测相应存储体的选择，并响应于来自命令数据总线的命令信号接收地址信号。 靠近地址数据总线和命令数据总线侧的电路比锁存接收数据的电路具有分层电源配置。

    Semiconductor memory device
    48.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06198679B1

    公开(公告)日：2001-03-06

    申请号：US09408717

    申请日：1999-09-29

    申请人： Teruhiko Nakasu ,  Shigeki Tomishima ,  Tsukasa Ooishi

    发明人： Teruhiko Nakasu ,  Shigeki Tomishima ,  Tsukasa Ooishi

    IPC分类号： G11C700

    CPC分类号： G11C7/1072 ,  G11C7/22

    摘要： The objective of the invention is to read and write data in synchronization with a high-speed clock signal. The pulse width of the timing control signal (FY signal), which determines the pulse width of the column select signal (YS signal), is enlarged in a data read operation and reduced in a data write operation. In this way, the activation pulse width of the column select signal is enlarged in a data read operation and reduced in a data write operation. Consequently, in a data read operation, the time for connecting a bit line pair to an input/output line pair becomes longer. The potential difference of the bit line pair can be completely transferred to the input/output line pair. Therefore, data can be read correctly in synchronization with a high-speed clock signal.

    摘要翻译： 本发明的目标是与高速时钟信号同步地读取和写入数据。 在数据读取操作中放大确定列选择信号（YS信号）的脉冲宽度的定时控制信号（FY信号）的脉冲宽度，并在数据写入操作中减小。 以这种方式，列选择信号的激活脉冲宽度在数据读取操作中被放大并且在数据写入操作中被减少。 因此，在数据读取操作中，将位线对连接到输入/输出线对的时间变长。 位线对的电位差可以完全传输到输入/输出线对。 因此，可以与高速时钟信号同步读取数据。

    Semiconductor memory device implementing multi-bank configuration with reduced number of signal lines
    49.
    发明授权
    Semiconductor memory device implementing multi-bank configuration with reduced number of signal lines 有权
    实现具有减少信号线数量的多存储体配置的半导体存储器件

    公开(公告)号：US06078542A

    公开(公告)日：2000-06-20

    申请号：US204282

    申请日：1998-12-03

    申请人： Shigeki Tomishima

    发明人： Shigeki Tomishima

    IPC分类号： G11C11/41 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C8/14 ,  G11C8/12

    摘要： A memory cell array in a semiconductor memory device according to the present invention is divided into a plurality of banks along the row-direction. Each bank is further divided into a plurality of sub blocks along the column-direction. Sub blocks belonging to the same group, in other words, sub blocks arranged adjacent to each other along the row-direction share the same row address. An accessing operation to an addressed memory cell is performed on the basis of a sub block. The activation of a sub block is performed by a control circuit provided for each of the sub blocks based on a signal activated for each of the banks and the same group based on an address signal.

    摘要翻译： 根据本发明的半导体存储器件中的存储单元阵列沿着行方向分成多个组。 每个存储体还沿着列方向被分成多个子块。 属于同一组的子块，换句话说，沿着行方向彼此相邻布置的子块共享相同的行地址。 基于子块执行对寻址的存储器单元的访问操作。 基于对于每个存储体和相同组基于地址信号激活的信号，通过为每个子块提供的控制电路来执行子块的激活。