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    METHOD AND APPARATUS FOR VECTOR SORTING
    41.
    发明申请
    METHOD AND APPARATUS FOR VECTOR SORTING 审中-公开

    公开(公告)号：US20200371791A1

    公开(公告)日：2020-11-26

    申请号：US16589118

    申请日：2019-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy David Anderson ,  Mujibur Rahman

    IPC: G06F9/30 ,  G06F7/24

    Abstract: A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

    Faster and More Efficient Different Precision Sum of Absolute Differences for Dynamically Configurable Block Searches for Motion Estimation
    43.
    发明申请
    Faster and More Efficient Different Precision Sum of Absolute Differences for Dynamically Configurable Block Searches for Motion Estimation 有权
    更快，更高效的动态可配置块搜索的绝对差异精度和的运动估计

    公开(公告)号：US20150082004A1

    公开(公告)日：2015-03-19

    申请号：US14327002

    申请日：2014-07-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

    IPC: G06F9/30

    CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

    Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

    Abstract translation: 本发明是在单个操作中形成多个绝对值（SAD）的数字信号处理器。 执行包括两组多行的绝对值操作之和的操作单元，每行产生SAD输出。 多个绝对值差分单元接收相应的压缩候选像素数据和压缩参考像素数据。 行夏天对行中的绝对值差单位的输出求和。 候选像素相对于参考像素相对于一组行中的每个后续行偏移一个像素。 两组行在包含在指令指定操作数中的候选像素的相对的两半上进行操作。 可以使用绝对差分单位和行夏季的进位链控制在不同的数据宽度上执行SAD操作。

    Processing device with vector transformation execution
    44.
    发明授权
    Processing device with vector transformation execution 有权

    公开(公告)号：US12182573B2

    公开(公告)日：2024-12-31

    申请号：US18370487

    申请日：2023-09-20

    Applicant: Texas Instruments Incorporated

    Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Joseph Zbiciak

    IPC: G06F9/38 ,  G06F9/30

    Abstract: An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.

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