公开(公告)号：US20230386905A1

公开(公告)日：2023-11-30

申请号：US18446183

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/76 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/7682 ,  H01L21/76 ,  H01L21/76834 ,  H01L23/5286 ,  H01L23/53295 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02172

Abstract: A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

公开(公告)号：US11824101B2

公开(公告)日：2023-11-21

申请号：US17705508

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi-On Chui ,  Kai-Hsuan Lee ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor substrate, an isolation feature over the semiconductor substrate, a fin protruding from the semiconductor substrate and through the isolation feature, a gate stack over and engaging the fin, and a gate spacer on sidewalls of the gate stack. A bottom portion of the sidewalls of the gate stack tilts inwardly towards the gate stack.

公开(公告)号：US11804486B2

公开(公告)日：2023-10-31

申请号：US17572212

申请日：2022-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/0274 ,  H01L21/3086 ,  H01L21/30604

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US11798884B2

公开(公告)日：2023-10-24

申请号：US17682884

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3213

CPC classification number: H01L23/5283 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/5226

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

公开(公告)号：US11791218B2

公开(公告)日：2023-10-17

申请号：US16879613

申请日：2020-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/26 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/26 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A method includes providing a structure having a substrate, first and second channel layers over the substrate, and first and second gate dielectric layers over the first and the second channel layers respectively. The method further includes forming a first dipole pattern over the first gate dielectric layer, the first dipole pattern having a first dipole material that is of a first conductivity type; forming a second dipole pattern over the second gate dielectric layer, the second dipole pattern having a second dipole material that is of a second conductivity type opposite to the first conductivity type; and annealing the structure such that elements of the first dipole pattern are driven into the first gate dielectric layer and elements of the second dipole pattern are driven into the second gate dielectric layer.

公开(公告)号：US20230326983A1

公开(公告)日：2023-10-12

申请号：US18329126

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L21/28097 ,  H01L21/28158 ,  H01L21/823475

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

公开(公告)号：US11777033B2

公开(公告)日：2023-10-03

申请号：US17133290

申请日：2020-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Hsun Wang ,  Chun-Hsiung Lin ,  Cheng-Ting Chung ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/66795

Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.

公开(公告)号：US20230307552A1

公开(公告)日：2023-09-28

申请号：US18328946

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Jia-Ni Yu ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Kuan-Lun Cheng

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/78696 ,  H01L29/66742 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78684 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02236 ,  H01L21/28185 ,  H01L21/823807 ,  H01L29/66545 ,  H01L29/66636 ,  H01L27/092

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

公开(公告)号：US20230299159A1

公开(公告)日：2023-09-21

申请号：US18324682

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning Ju ,  Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L21/823431 ,  H01L29/785 ,  H01L2029/7858

Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.

公开(公告)号：US11764281B2

公开(公告)日：2023-09-19

申请号：US17874892

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Ning Yao ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/49 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/4991 ,  H01L21/28123 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Fin-like field effect transistors (FinFETs) and methods of fabrication thereof are disclosed herein. The FinFETs disclosed herein have gate air spacers integrated into their gate structures. An exemplary transistor includes a fin and a gate structure disposed over the fin between a first epitaxial source/drain feature and a second epitaxial source/drain feature. The gate structure includes a gate electrode, a gate dielectric, and gate air spacers disposed between the gate dielectric and sidewalls of the gate electrode.