公开(公告)号：US20200098759A1

公开(公告)日：2020-03-26

申请号：US16370258

申请日：2019-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308 ,  H01L21/28

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

公开(公告)号：US20200043919A1

公开(公告)日：2020-02-06

申请号：US16215676

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Mao-Lin Huang ,  Zhi-Chang Lin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

公开(公告)号：US12272634B2

公开(公告)日：2025-04-08

申请号：US18301757

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a source/drain (S/D) region, one or more dielectric layers over the S/D region, one or more semiconductor channel layers connected to the S/D region, an isolation structure under the S/D region and the one or more semiconductor channel layers, and a via under the S/D region and electrically connected to the S/D region. A lower portion of the via is surrounded by the isolation structure and an upper portion of the via extends vertically between the S/D region and the isolation structure.

公开(公告)号：US20240339526A1

公开(公告)日：2024-10-10

申请号：US18750379

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US20240322041A1

公开(公告)日：2024-09-26

申请号：US18674634

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76829 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US11996481B2

公开(公告)日：2024-05-28

申请号：US17322267

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/76829 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US11978802B2

公开(公告)日：2024-05-07

申请号：US16218493

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Wei Hsu ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/76832 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

公开(公告)号：US11948973B2

公开(公告)日：2024-04-02

申请号：US17402985

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Huan-Chieh Su ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

公开(公告)号：US20240105719A1

公开(公告)日：2024-03-28

申请号：US18524934

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

公开(公告)号：US20240021616A1

公开(公告)日：2024-01-18

申请号：US18356677

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/66795 ,  H01L21/823418 ,  H01L29/0653 ,  H01L21/823431 ,  H01L29/7851

Abstract: A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.