公开(公告)号：US20140264725A1

公开(公告)日：2014-09-18

申请号：US13854507

申请日：2013-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

Abstract: The embodiments described provide methods and semiconductor device areas for etching an active area region on a semiconductor body and epitaxially depositing a semiconductor layer overlying the active region. The methods enable the mitigation or elimination of problems encountered in subsequent manufacturing associated with STI divots.

Abstract translation: 所描述的实施例提供了用于蚀刻半导体主体上的有源区域并且外延沉积覆盖有源区域的半导体层的方法和半导体器件区域。 这些方法可以减轻或消除随后与STI科技相关的制造过程中遇到的问题。

公开(公告)号：US12199034B2

公开(公告)日：2025-01-14

申请号：US18454209

申请日：2023-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Kuang ,  Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Bao-Ru Young ,  Wang-Jung Hsueh ,  Pang-Chi Wu

IPC: H01L23/522 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

公开(公告)号：US20240363427A1

公开(公告)日：2024-10-31

申请号：US18764973

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

公开(公告)号：US12009399B2

公开(公告)日：2024-06-11

申请号：US17222100

申请日：2021-04-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Jyun Huang ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/66545 ,  H01L2029/7858

Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.

公开(公告)号：US11996329B2

公开(公告)日：2024-05-28

申请号：US18162841

申请日：2023-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hsiung Wang ,  Bao-Ru Young ,  Tung-Heng Hsieh

IPC: H01L21/768 ,  G06F30/39 ,  G06F30/398 ,  H01L21/66 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  G06F119/18 ,  H01L27/118

CPC classification number: H01L21/76892 ,  G06F30/39 ,  G06F30/398 ,  H01L21/76895 ,  H01L22/20 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0207 ,  G06F2119/18 ,  H01L2027/11881

Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC layout having a first pattern layer that includes first source/drain (S/D) contacts and second S/D contacts, the first and second S/D contacts are spaced away from each other by a spacing along a first direction, and each of the first and second S/D contacts have elongated shapes extending lengthwise in a second direction perpendicular to the first direction. The method includes constructing a conductive feature on a second pattern layer of the IC layout, the conductive feature having an initial rectangular shape with a length and a width, the length extending along the first direction. And the method includes modifying the conductive feature to form a modified conductive feature that is overlapped with the first S/D contacts and distanced away from the second S/D contacts.

公开(公告)号：US20230411280A1

公开(公告)日：2023-12-21

申请号：US18454209

申请日：2023-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao Kuang ,  Tung-Heng Hsieh ,  Sheng-Hsiung Wang ,  Bao-Ru Young ,  Wang-Jung Hsueh ,  Pang-Chi Wu

IPC: H01L23/522 ,  G06F30/398 ,  G06F30/392 ,  G06F30/3953

CPC classification number: H01L23/5226 ,  G06F30/3953 ,  G06F30/392 ,  G06F30/398

Abstract: A device includes a semiconductor substrate, an active region over the semiconductor substrate extending lengthwise in a first direction, a gate structure over the active region extending lengthwise in a second direction perpendicular to the first direction, a source feature and a drain feature on the active region and interposed by the gate structure, a source contact on the source feature, a drain contact on the drain feature, and a via rail over the substrate spaced from the active region. The via rail includes a main portion extending lengthwise in the first direction having a sidewall surface facing opposite the end surface of the drain contact, and a jog via extending from the main portion along the second direction and having a sidewall surface facing the second direction, each of the main portion and the jog via contacting the source contact.

公开(公告)号：US20230377982A1

公开(公告)日：2023-11-23

申请号：US18361622

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Sheng Fan ,  Chun-Yen Lin ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L21/823437 ,  H01L29/6681 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/845 ,  H01L29/785

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.

公开(公告)号：US11507725B2

公开(公告)日：2022-11-22

申请号：US17195136

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young ,  Yung Feng Chang

IPC: G06F30/398 ,  G06F30/39 ,  G06F30/367 ,  G03F1/36 ,  G06F119/06

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

公开(公告)号：US20220367441A1

公开(公告)日：2022-11-17

申请号：US17876954

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung Feng Chang ,  Chun-Chia Hsu ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L27/02 ,  H01L29/08 ,  H01L27/092

Abstract: A semiconductor structure includes a substrate having a first well of a first conductivity type and a second well of a second conductivity type. From a top view, the first well includes first and seconds edges extending along a first direction. The second edge has multiple turns, resulting in the first well having a protruding section and a recessed section. The semiconductor structure further includes a first source/drain feature over the protruding section and a second source/drain feature over a main body of the first well. The first source/drain feature is of the first conductivity type. The second source/drain feature is of the second conductivity type. The first and the second source/drain features are generally aligned along a second direction perpendicular to the first direction from the top view.

公开(公告)号：US10832958B2

公开(公告)日：2020-11-10

申请号：US16397938

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Sheng Fan ,  Chun-Yen Lin ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L27/088 ,  H01L29/78

Abstract: A method and structure for mitigating leakage current in devices that include a continuous active region. In some embodiments, a threshold voltage at the cell boundary is increased by changing a photomask logic operation (LOP) to reverse a threshold voltage type at the cell boundary. Alternatively, in some cases, the threshold voltage at the cell boundary is increased by performing a threshold voltage implant (e.g., an ion implant) at the cell boundary, and into a dummy gate disposed at the cell boundary. Further, in some embodiments, the threshold voltage at the cell boundary is increased by use of a silicon germanium (SiGe) channel at the cell boundary. In some cases, the SiGe may be disposed within the substrate at the cell boundary and/or the SiGe may be part of the dummy gate disposed at the cell boundary.