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公开(公告)号：US10957704B2
公开(公告)日：2021-03-23
申请号：US16734691
申请日：2020-01-06
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Ya-Chen Kao , Yi Hsien Lu
IPC分类号： H01L29/792 , H01L27/11573 , H01L29/66 , H01L29/423 , H01L29/51 , H01L21/8234 , H01L27/092 , H01L27/088
摘要： The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.
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公开(公告)号：US20200303629A1
公开(公告)日：2020-09-24
申请号：US16899700
申请日：2020-06-12
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
摘要： The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.
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公开(公告)号：US10686125B2
公开(公告)日：2020-06-16
申请号：US16222031
申请日：2018-12-17
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
摘要： The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.
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公开(公告)号：US20200098440A1
公开(公告)日：2020-03-26
申请号：US16410308
申请日：2019-05-13
发明人： Harry-Hak-Lay Chuang , Tien-Wei Chiang , Wen-Chun You , Yi-Chieh Chiu , Yu-Lin Chen , Jian-Cheng Huang , Chang-Hung Chen
摘要： Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction. The broken-down state corresponds to a one-time programmed state and is not susceptible to high-temperature change, even at small sizes.
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公开(公告)号：US20200020848A1
公开(公告)日：2020-01-16
申请号：US16580419
申请日：2019-09-24
摘要： Some embodiments relate to a method for manufacturing a magnetoresistive random-access memory (MRAM) cell. The method includes forming a spacer layer surrounding at least a magnetic tunnel junction (MTJ) layer and a top electrode of the MRAM cell; etching the spacer layer to expose a top surface of the top electrode and a top surface of a spacer formed by the spacer layer; forming an upper etch stop layer over the top electrode top surface and the spacer top surface; and forming an upper metal layer in contact with the top electrode top surface of the MRAM cell. A width of the upper etch stop layer is greater than a width of a bottom surface of the upper metal layer.
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公开(公告)号：US10522740B2
公开(公告)日：2019-12-31
申请号：US15991004
申请日：2018-05-29
摘要： Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in contact with the upper metal layer. A sidewall spacer surrounds an outer periphery of the top electrode. An etch stop layer is disposed on top of an outer periphery of the spacer top surface and surrounding an outer periphery of the bottom surface of the upper metal layer. The etch stop layer overhangs the outer periphery of the spacer top surface.
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公开(公告)号：US10516026B2
公开(公告)日：2019-12-24
申请号：US16166603
申请日：2018-10-22
IPC分类号： H01L29/423 , H01L27/11521 , H01L27/1157 , H01L27/11524 , H01L27/11568 , H01L29/66 , H01L21/28 , H01L29/792 , H01L29/51
摘要： The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.
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48.发明申请公开(公告)号：US20190386061A1
公开(公告)日：2019-12-19
申请号：US16379901
申请日：2019-04-10
发明人： Kuo-An Liu , Chung-Cheng Wu , Harry-Hak-Lay Chuang , Gwan-Sin Chang , Tien-Wei Chiang , Zhiqiang Wu , Chia-Hsiang Chen
摘要： In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.
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公开(公告)号：US20190123264A1
公开(公告)日：2019-04-25
申请号：US16222031
申请日：2018-12-17
发明人： Harry-Hak-Lay Chuang , Hung Cho Wang , Tong-Chern Ong , Wen-Ting Chu , Yu-Wen Liao , Kuei-Hung Shen , Kuo-Yuan Tu , Sheng-Huang Huang
CPC分类号： H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1675
摘要： The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.
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公开(公告)号：US20190123184A1
公开(公告)日：2019-04-25
申请号：US16227931
申请日：2018-12-20
发明人： Harry-Hak-Lay Chuang , Cheng-Cheng Kuo , Chi-Wen Liu , Ming Zhu
IPC分类号： H01L29/66 , H01L29/739 , H01L21/324 , H01L29/423 , H01L21/3065 , H01L21/308 , H01L21/265 , H01L29/06 , H01L29/786
摘要： Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.
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