公开(公告)号：US20170243915A1

公开(公告)日：2017-08-24

申请号：US15591722

申请日：2017-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Shih Pei Chou ,  Chih-Yu Lai ,  Sheng-Chau Chen ,  Chih-Ta Chen ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L21/823878 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14687 ,  H01L33/20

Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

公开(公告)号：US12266579B2

公开(公告)日：2025-04-01

申请号：US17461004

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Sheng-Chau Chen ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai

IPC: H01L21/02 ,  C23C16/46 ,  C23C16/50 ,  C23C16/52 ,  H01J37/32 ,  H01L21/66

Abstract: A thin-film deposition system includes a top plate positioned above a wafer and configured to generate a plasma during a thin-film deposition process. The system includes a gap sensor configured to generate sensor signals indicative of a gap between the wafer and the top plate. The system includes a control system configured to adjust the gap during the thin-film deposition process responsive to the sensor signals.

公开(公告)号：US12176372B2

公开(公告)日：2024-12-24

申请号：US17197291

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Ming-Che Lee

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards a pixel sensor. The pixel sensor includes a substrate having a front-side opposite a back-side. An image sensor element comprises an active layer disposed within the substrate, where the active layer comprises germanium. An anti-reflective coating (ARC) structure overlies the back-side of the substrate. The ARC structure includes a first dielectric layer overlying the back-side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer. A first index of refraction of the first dielectric layer is less than a second index of refraction of the second dielectric layer, and a third index of refraction of the third dielectric layer is less than the first index of refraction.

公开(公告)号：US11984431B2

公开(公告)日：2024-05-14

申请号：US18156848

申请日：2023-01-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Yung-Lung Lin ,  Zhi-Yang Wang ,  Sheng-Chau Chen ,  Cheng-Hsien Chou

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L24/06 ,  H01L25/50

Abstract: A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

公开(公告)号：US11925033B2

公开(公告)日：2024-03-05

申请号：US17217000

申请日：2021-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B61/22 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US11869916B2

公开(公告)日：2024-01-09

申请号：US17097360

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Wei Liang ,  Sheng-Chau Chen ,  Hsun-Chung Kuang ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/1462 ,  H01L27/14685 ,  H01L27/14698

Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

公开(公告)号：US11705360B2

公开(公告)日：2023-07-18

申请号：US17197330

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsien Chou ,  Sheng-Chau Chen ,  Tzu-Jui Wang ,  Sheng-Chan Li

IPC: H01L21/762 ,  H01L27/146

CPC classification number: H01L21/76224 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685

Abstract: In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.

公开(公告)号：US20220238568A1

公开(公告)日：2022-07-28

申请号：US17336852

申请日：2021-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

公开(公告)号：US20220223634A1

公开(公告)日：2022-07-14

申请号：US17144757

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che Wei Yang ,  Sheng-Chan Li ,  Tsun-Kai Tsao ,  Chih-Cheng Shih ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.

公开(公告)号：US11367623B2

公开(公告)日：2022-06-21

申请号：US17070461

申请日：2020-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Cheng-Tai Hsiao ,  Cheng-Yuan Tsai ,  Hsun-Chung Kuang ,  Yao-Wen Chang

IPC: H01L45/00 ,  H01L21/311 ,  H01L21/3105 ,  H01L43/02 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12

Abstract: A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.