公开(公告)号：US10515827B2

公开(公告)日：2019-12-24

申请号：US15874541

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC: H01L21/48 ,  H01L25/10 ,  H01L23/498 ,  H01L21/52 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

Abstract: A method for forming a chip package is provided. The method includes disposing a chip over a redistribution structure. The redistribution structure includes a first insulating layer and a first wiring layer, and the first wiring layer is in the first insulating layer and electrically connected to the chip. The method includes bonding an interposer substrate to the redistribution structure through a conductive structure. The chip is between the interposer substrate and the redistribution structure. The interposer substrate has a recess adjacent to the redistribution structure. A first portion of the chip is in the recess. The interposer substrate includes a substrate and a conductive via structure, and the conductive via structure passes through the substrate and is electrically connected to the first wiring layer through the conductive structure.

公开(公告)号：US20190139896A1

公开(公告)日：2019-05-09

申请号：US15806342

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a RDL structure and a protection layer. The die includes a first surface and a second surface opposite to each other. The encapsulant is aside the die. The RDL structure is electrically connected to the die though a plurality of conductive bumps. The RDL structure is underlying the second surface of the die and the encapsulant. The protection layer is located over the first surface of the die and the encapsulant. The protection layer is used for controlling the warpage of the package structure.

公开(公告)号：US10276484B2

公开(公告)日：2019-04-30

申请号：US15937188

申请日：2018-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Der-Chyang Yeh ,  Chiung-Han Yeh

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

公开(公告)号：US20240387378A1

公开(公告)日：2024-11-21

申请号：US18787615

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/532 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacture are provided wherein multiple integrated passive devices are integrated together utilizing an integrated fan out process in order to form a larger device with a smaller footprint. In particular embodiments the multiple integrated passive devices are capacitors which, once stacked together, can be utilized to provide a larger overall capacitance than any single passive device can obtain with a similar footprint.

公开(公告)号：US20240371843A1

公开(公告)日：2024-11-07

申请号：US18775285

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes bonding a first package component and a second package component to an interposer. The first package component includes a core device die, and the second package component includes a memory die. An Independent Passive Device (IPD) die is bonded directly to the interposer. The IPD die is electrically connected to the first package component through a first conductive path in the interposer. A package substrate is bonded to the interposer die. The package substrate is on an opposing side of the interposer than the first package component and the second package component.

公开(公告)号：US12113025B2

公开(公告)日：2024-10-08

申请号：US17881981

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Hsien-Wen Liu ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Po-Yao Lin

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/76885 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5384 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/95 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

公开(公告)号：US11887952B2

公开(公告)日：2024-01-30

申请号：US17875312

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L24/08 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02145 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1058 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19011 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2224/13644 ,  H01L2924/00014 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2924/1436 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

公开(公告)号：US11443993B2

公开(公告)日：2022-09-13

申请号：US16984382

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Feng-Cheng Hsu ,  Shuo-Mao Chen

IPC: H01L23/13 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate over the package substrate, and multiple semiconductor devices over the interposer substrate. The interposer substrate also has one or more cavities to receive or accommodate additional semiconductor devices that are not allowed to be mounted on the surface of the interposer substrate. The cavities enable a thinner overall package structure. Some semiconductor devices received in the interposer substrate cavities may also be electrically connected to the interposer substrate and/or the semiconductor devices over the interposer substrate in order to improve the electrical performance of the overall package structure.

公开(公告)号：US11417620B2

公开(公告)日：2022-08-16

申请号：US17025831

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H05K7/00 ,  H05K1/11 ,  H05K1/14 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538

Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

公开(公告)号：US20220216192A1

公开(公告)日：2022-07-07

申请号：US17701083

申请日：2022-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L25/18 ,  H01L27/01 ,  H01L23/31 ,  H01L25/065 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.