公开(公告)号：US06710730B2

公开(公告)日：2004-03-23

申请号：US09900018

申请日：2001-07-09

申请人： Hisashi Harada ,  Takahiro Miki

发明人： Hisashi Harada ,  Takahiro Miki

IPC分类号： H03M178

CPC分类号： H03M1/068 ,  H03M1/46 ,  H03M1/76

摘要： A ladder resistor includes a first resistor group including a number of resistors connected in series and generating a number of reference voltages, and a second resistor group including a same number of resistors connected in series as the plurality of resistors included in the first resistor group, and generating a number of reference voltages. The plurality of resistors included in the second resistor group corresponds to the plurality of resistors included in the first resistor group, respectively. Each of the plurality of resistors included in the first resistor group and a corresponding one of the plurality of resistors included in the second resistor group, that is, each resistor pair is symmetric with respect to a given point. The first resistor group is separated from the second resistor group so that they face each other with the point between.

摘要翻译： 梯形电阻器包括包括串联连接的多个电阻器并产生多个参考电压的第一电阻器组和包括与包括在第一电阻器组中的多个电阻器串联连接的相同数量的电阻器的第二电阻器组， 并产生多个参考电压。 包括在第二电阻器组中的多个电阻分别对应于包括在第一电阻器组中的多个电阻器。 包括在第一电阻器组中的多个电阻器中的每一个以及包括在第二电阻器组中的多个电阻器中的相应一个电阻器，即每个电阻器对相对于给定点是对称的。 第一电阻器组与第二电阻器组分开，使得它们彼此面对。

公开(公告)号：US06556039B2

公开(公告)日：2003-04-29

申请号：US09962191

申请日：2001-09-26

申请人： Hideo Nagano ,  Takahiro Miki

发明人： Hideo Nagano ,  Takahiro Miki

IPC分类号： H03K1714

CPC分类号： H04L25/0278

摘要： An impedance adjustment circuit achieves impedance matching between a terminal resistor in a reception-side semiconductor device and a transmission line. A reference resistor has a first resistance proportional to characteristic impedance of the transmission line. This reference resistor is external to the reception-side semiconductor device. Furthermore, the terminal resistor includes a resistor having a second resistance and an ON resistance of an MOS transistor. The resistance of the terminal resistor is adjusted by referring to the reference resistor.

摘要翻译： 阻抗调整电路实现接收侧半导体装置中的端子电阻与传输线之间的阻抗匹配。 参考电阻具有与传输线的特性阻抗成比例的第一电阻。 该参考电阻器在接收侧半导体器件的外部。 此外，端子电阻器包括具有MOS晶体管的第二电阻和导通电阻的电阻器。 通过参考电阻调节端子电阻的电阻。

公开(公告)号：US5801705A

公开(公告)日：1998-09-01

申请号：US672417

申请日：1996-06-28

申请人： Yoshiyuki Kato ,  Masatoshi Kameyama ,  Takahiro Miki

发明人： Yoshiyuki Kato ,  Masatoshi Kameyama ,  Takahiro Miki

IPC分类号： H04N13/04 ,  G06T19/00 ,  G09G1/06 ,  G09G5/06 ,  G09G5/14 ,  G09G5/36 ,  G09G5/397 ,  G09G5/399 ,  H04N13/00 ,  G06T15/00

CPC分类号： H04N13/0497 ,  G06T15/00 ,  G09G1/06 ,  G09G3/003 ,  G09G5/06 ,  G09G5/14 ,  G09G5/397 ,  H04N13/0048 ,  H04N13/0051 ,  H04N13/0055 ,  H04N13/0275 ,  H04N13/0438 ,  H04N13/0456 ,  H04N13/047 ,  H04N13/0285

摘要： A graphic display unit makes it possible for a stereo display or blink operation to be implemented on a window system with each window having an arbitrary contour, and on a window by window basis. The graphic display unit of this invention comprises a frame buffer for a right eye, a frame buffer for a left eye, a window-id buffer which stores a window-id corresponding to the contour and position of windows on the frame buffer, a look-up table which stores control information related to stereo display and is accessed based on a window-id, a frame counter that issues the timing of switching frame buffers, a stereo display control circuit for switching buffers based on signals from both the look-up table and from the frame counter, and stereo viewer that controls shutters for a right eye and a left eye.

摘要翻译： 图形显示单元使得可以在具有任意轮廓的每个窗口的窗口系统上以窗口为基础在窗口系统上实现立体显示或眨眼操作。 本发明的图形显示单元包括用于右眼的帧缓冲器，用于左眼的帧缓冲器，窗口ID缓冲器，其存储与帧缓冲器上的轮廓和窗口的位置相对应的窗口ID，外观 存储与立体显示相关的控制信息的表，并且基于窗口id访问，发出切换帧缓冲器的定时的帧计数器，用于根据来自查找器的信号切换缓冲器的立体显示控制电路 桌子和框架计数器，以及用于控制右眼和左眼的百叶窗的立体观看器。

公开(公告)号：US5689258A

公开(公告)日：1997-11-18

申请号：US532315

申请日：1995-09-21

申请人： Yasuyuki Nakamura ,  Hiroyuki Kouno ,  Takahiro Miki

发明人： Yasuyuki Nakamura ,  Hiroyuki Kouno ,  Takahiro Miki

IPC分类号： H03M1/08 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0863 ,  H03M1/747

摘要： A digital-analog converter has unit current source cells each having a differential switch circuit and a constant current source. The differential switch circuit made of two switches is driven by a pair of complementary driving circuits controlled by a bit signal and the inverted bit signal corresponding to that signal and entered simultaneously. The constant current source outputs a constant current to a first and a second current output terminal via the switch circuit. The signals for controlling the driving circuits that drive the switches are such that the delay time for the switch closing operation will be longer than the delay time for the switch opening operation. As a result, the cross point of the two signals to open and close the switches in a complementary manner becomes greater than the median between the maximum and minimum signal levels. That is, even when the threshold value of a currently switching transistor is greater than a median, that value may be arranged to match the median, whereby the furnished switching transistors are not turned on or off simultaneously.

摘要翻译： 数模转换器具有单元电流源单元，每个单元具有差分开关电路和恒流源。 由两个开关构成的差分开关电路由一对由位信号控制的互补驱动电路和对应于该信号的反相位信号驱动并同时输入。 恒流源通过开关电路向第一和第二电流输出端输出恒定电流。 用于控制驱动开关的驱动电路的信号使得开关闭合操作的延迟时间将长于开关操作的延迟时间。 结果，以互补方式打开和闭合开关的两个信号的交叉点变得大于最大和最小信号电平之间的中值。 也就是说，即使当当前开关晶体管的阈值大于中值时，也可以将该值设置为与中值相匹配，由此所提供的开关晶体管不会同时导通或截止。

公开(公告)号：US5010338A

公开(公告)日：1991-04-23

申请号：US260126

申请日：1988-10-18

申请人： Takahiro Miki ,  Shiro Hosotani

发明人： Takahiro Miki ,  Shiro Hosotani

IPC分类号： H03K5/08 ,  H03K5/24 ,  H03M1/36

CPC分类号： H03K5/249 ,  H03M1/365

摘要： A comparator circuit capable of high-speed and accurate operation is disclosed. The comparator circuit includes an amplifier section 4, an inverter 5 connected to the output of the amplifier section 4, and a switching circuit 11 connected across the inverter 5. The amplifier section 4 contains a capacitor 1, an inverter 2 and a switching circuit 3 connected across the inverter 2. Coupled to the input of the amplifier section 4 are switching circuits 8 and 9 for supplying voltages V.sub.1 and V.sub.2 to be compared under timing control. During the first half cycle of comparing operation, the switching circuits 8, 3 and 11 are turned on while the switch circuit 9 is turned off. During the second half cycle of comparing operation, the switching circuit 9 is turned on while the switching circuits 8, 3 and 11 are turned off. The inverter 5, being short circuited by the switching circuit 11, produces a predetermined intermediate voltage during the first half of operating cycle, which is effective to generate voltage outputs accurately and exactly representing the compared results during the second half of the operating cycle.

摘要翻译： 公开了一种能够高速且精确地操作的比较器电路。 比较器电路包括放大器部分4，连接到放大器部分4的输出的反相器5和连接在反相器5两端的开关电路11.放大器部分4包含电容器1，反相器2和开关电路3 连接到逆变器2.耦合到放大器部分4的输入端，是用于提供电压V1和V2的开关电路8和9，以在定时控制下进行比较。 在比较操作的前半周期期间，开关电路8,3和11在开关电路9断开时导通。 在比较操作的第二个半周期期间，开关电路9导通，而开关电路8,3和11断开。 由开关电路11短路的逆变器5在操作周期的前半部分期间产生预定的中间电压，这对于在操作周期的后半期期间精确地和准确地表示比较结果来产生电压输出是有效的。

公开(公告)号：US4968988A

公开(公告)日：1990-11-06

申请号：US274437

申请日：1988-11-22

申请人： Takahiro Miki ,  Hideki Ando

发明人： Takahiro Miki ,  Hideki Ando

IPC分类号： H03M1/12 ,  H03M1/06

CPC分类号： H03M1/0651 ,  H03M1/1215

摘要： A time interleaved analog-to-digital converter includes a plurality of analog-to-digital subconverters which are monolithically integrated in an array on a semiconductor chip and are sequentially activated into sampling and conversion operation in the time interleaved fashion for converting a received analog signal into a digital form. If an analog-to-digital subconverter in the i-th row of the j-th column of the array is activated at one sampling time in the sequential activation, an analog-to-digital subconverter in the k-th row of the l-th column is subsequently activated, where i, k, j and l bear the relations expressed by:i-2.ltoreq.k.ltoreq.i+2 and j-2.ltoreq.l.ltoreq.j+2.The sequential activation of the analog-to-digital subconverter array assures that the analog-to-digital subconverters disposed in physical proximity to one another are successively activated, thus greatly improving the differential linearity of the analog-to-digital converter characteristics.

摘要翻译： 时间交织的模数转换器包括多个模数转换子转换器，它们单片集成在半导体芯片上的阵列中，并以时间交错方式被顺序激活成采样和转换操作，用于转换接收的模拟信号 成为数字形式。 如果阵列的第j列的第i行中的模数转换子转换器在顺序激活中的一个采样时间被激活，则l的第k行中的模数转换子转换器 随后激活第i列，其中i，k，j和l具有由以下公式表示的关系：i-2

公开(公告)号：US4918451A

公开(公告)日：1990-04-17

申请号：US265223

申请日：1988-11-01

申请人： Hideki Ando ,  Takahiro Miki

发明人： Hideki Ando ,  Takahiro Miki

IPC分类号： H03M1/36 ,  H03M1/00

CPC分类号： H03M1/0809 ,  H03M1/365

摘要： A reference voltage is divided by a plurality of resistors (6), the respective voltages and an analogue input voltage being compared with each other by comparators (7). An output of each of the comparators is applied to a data transfer circuit (13) of a hand shake type and latched. The data transfer circuit shifts discontinuous portions of logic which appeared in latched data. Therefore, simultaneous selection of a plurality of addresses in an encoder (10) is avoided.

摘要翻译： 参考电压由多个电阻器（6）分压，各个电压和模拟输入电压通过比较器（7）相互比较。 每个比较器的输出被施加到手抖动类型的数据传送电路（13）并被锁存。 数据传输电路移动出现在锁存数据中的逻辑不连续部分。 因此，避免了编码器（10）中的多个地址的同时选择。

公开(公告)号：US4723194A

公开(公告)日：1988-02-02

申请号：US911434

申请日：1986-09-25

申请人： Yasuyuki Nakamura ,  Takahiro Miki

发明人： Yasuyuki Nakamura ,  Takahiro Miki

IPC分类号： H01L27/04 ,  G11C11/24 ,  H01G4/38 ,  H01L21/822

CPC分类号： G11C11/24 ,  H01G4/385

摘要： A structure of a capacitor circuit in accordance with the present invention comprises a plurality of capacitors formed on a semiconductor or conductor substrate in a manner in which insulating films and electrodes are provided alternately. This structure is characterized in that: there are provided a first capacitor and a second capacitor adjacent to each other; the first capacitor and the second capacitor comprise, respectively, first electrodes formed on the substrate through the first insulating film, second electrodes formed on the first electrodes through the second insulating film and third electrodes formed on the second electrodes through the third insulating film, the third electrode of the first capacitor being connected to the second electrode of the second capacitor.

摘要翻译： 根据本发明的电容器电路的结构包括以交替设置绝缘膜和电极的方式形成在半导体或导体基板上的多个电容器。 该结构的特征在于：提供了彼此相邻的第一电容器和第二电容器; 第一电容器和第二电容器分别包括通过第一绝缘膜形成在基板上的第一电极，通过第二绝缘膜形成在第一电极上的第二电极和通过第三绝缘膜形成在第二电极上的第三电极， 第一电容器的第三电极连接到第二电容器的第二电极。

公开(公告)号：US20140015504A1

公开(公告)日：2014-01-16

申请号：US14009715

申请日：2012-04-09

申请人： Shinya Sano ,  Masashi Horiguchi ,  Takahiro Miki ,  Mitsuru Hiraki

发明人： Shinya Sano ,  Masashi Horiguchi ,  Takahiro Miki ,  Mitsuru Hiraki

IPC分类号： H02M3/158

CPC分类号： G05F3/267 ,  G05F3/20 ,  G05F3/26 ,  G05F3/30 ,  H02M3/158

摘要： A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.

摘要翻译： 其中放大器的偏移对输出电压的影响减小的电压产生电路具有在相同电位的发射极端子的第一和第二双极晶体管（Q1，Q2）。 Q1的基极端子设置在Q2的集电极侧。 第一电阻元件将Q2的集电极侧与Q2的基极侧连接; 并且第二电阻元件（R1）将Q1的集电极侧连接到R2。 第三电阻元件（R3）将Q2的基极端子与发射极端子的电位相连。 放大器（A1）输出基于Q1和Q2的集电极侧之间的电压差的电压; 电压电流转换部（MP1，MP2）将放大器输出转换为R1和R2的连接节点的电流。 然后基于所产生的电流输出电压。

公开(公告)号：US08456045B2

公开(公告)日：2013-06-04

申请号：US13057875

申请日：2010-03-31

申请人： Koji Hayashi ,  Makoto Tomita ,  Shinichi Kojima ,  Ryuichi Hasegawa ,  Takahiro Miki

发明人： Koji Hayashi ,  Makoto Tomita ,  Shinichi Kojima ,  Ryuichi Hasegawa ,  Takahiro Miki

IPC分类号： H02K9/00

CPC分类号： H02K9/19 ,  B60L3/0061 ,  B60L11/14 ,  B60L15/2009 ,  B60L2240/12 ,  B60L2240/36 ,  B60L2240/421 ,  B60L2240/441 ,  F16H57/0412 ,  F16H57/045 ,  F16H57/0476 ,  H02K16/00 ,  H02K51/00 ,  Y02T10/641 ,  Y02T10/645 ,  Y02T10/70 ,  Y02T10/7077 ,  Y02T10/72 ,  Y02T10/7275

摘要： A heat-generating portion cooling structure of vehicle drive apparatus that sufficiently supplies cooling oil to heat-generating portions to enhance efficiency of the vehicle drive apparatus when the heat-generating portions generate maximum heat includes drawing means for drawing oil in a case into a catch tank, and an oil circulation passage for circulating the oil through the catch tank while supplying the oil to first and second heat-generating portions. The oil circulation passage includes a first passage for the oil to flow to the first heat-generating portion when the oil surface in the catch tank is at a first height and a second passage for the oil to flow to the second heat-generating portion when the oil surface is at a second height lower than the first height, and more amount of oil flows to the second heat-generating portion than to the first heat-generating portion when the oil surface is low.

摘要翻译： 当发热部产生最大热量时，将驱动装置的冷却油向发热部充分供给以提高车辆驱动装置的效率的发热部冷却结构，包括将壳体内的油抽入捕集器 罐和油循环通道，用于在将油供应到第一和第二发热部分的同时使油通过捕集罐。 油循环通道包括第一通道，用于当捕集罐中的油表面处于第一高度时油流向第一发热部分，并且第二通道用于油流到第二发热部分时， 油表面处于比第一高度低的第二高度，并且当油表面低时，更多的油流到第二发热部分而不是第一发热部分。