公开(公告)号：US20060138568A1

公开(公告)日：2006-06-29

申请号：US11359291

申请日：2006-02-23

Applicant: Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

Inventor： Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

IPC: H01L29/76

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11546 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7835 ,  Y10S438/981

Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.

Abstract translation: 能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。 可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

公开(公告)号：US06956546B1

公开(公告)日：2005-10-18

申请号：US09684616

申请日：2000-10-10

Applicant: Takashi Hashimoto ,  Yasutaka Inanaga

Inventor： Takashi Hashimoto ,  Yasutaka Inanaga

IPC: G09G3/28

CPC classification number: G09G3/293 ,  G09G3/294 ,  G09G3/2983 ,  G09G2310/0218 ,  H01J2211/245

Abstract: Row electrodes Xi (i=1 to n) are arranged over portions close to right and left ends of a PDP, and column electrodes Wj (j=1 to m) are arranged over portions close to upper and lower ends thereof to grade-separately intersect with the row electrodes Xi. The column electrodes Wj and Wm+1−j are connected in common. Row electrodes YL1 to YLn extending over a portion close to the left end and a portion close to the center and row electrodes YR1 to YRn extending over a portion close to the right end and a portion close to the center are arranged alternately with row electrodes X1 to Xn. A scan pulse Vax1 is successively applied to the row electrodes Xi and a voltage Vaw1 based on image data is applied to each column electrode Wj in synchronization with the application of the pulse Vax1 in a first address period. In this period, a subscan pulse Vay1 is applied to the row electrodes YL1 to YLn while the row electrodes YR1 to YRn are set to a ground potential. In a second address period, the voltages applied to the aforementioned row electrodes YL1 to YLn and the row electrodes YR1 to YRn are exchanged. Thus, reduction of the cost for a plasma display device is attained by reducing the number of driving ICs for the column electrodes.

Abstract translation: 行电极Xi（i = 1〜n）配置在靠近PDP左右两端的部分上，列电极Wj（j = 1〜m）配置在接近其上端和下端的部分上，以分级分开 与行电极Xi交叉。 列电极Wj和Wm + 1-j共同连接。 在靠近左端的部分和靠近中心的部分延伸的行电极YL 1〜YLn和在靠近右端的部分和靠近中心的部分延伸的行电极YR 1〜YRn交替地排列 电极X 1〜Xn。 扫描脉冲Vax 1被连续地施加到行电极Xi，并且基于图像数据的电压Vaw 1与在第一寻址周期中施加脉冲Vax 1同步地施加到每个列电极Wj。 在此期间，对行电极YL 1〜YLn施加副扫描脉冲Vay1，同时将行电极YR 1〜YRn设定为接地电位。 在第二寻址期间，交替施加到上述行电极YL 1〜YLn和行电极YR 1〜YRn的电压。 因此，通过减少列电极的驱动IC的数量来实现等离子体显示装置的成本的降低。

公开(公告)号：US06905934B2

公开(公告)日：2005-06-14

申请号：US10086689

申请日：2002-03-04

Applicant: Takashi Hashimoto ,  Kouji Mikami ,  Tsutomu Udo ,  Masao Kondo ,  Eiji Oue

Inventor： Takashi Hashimoto ,  Kouji Mikami ,  Tsutomu Udo ,  Masao Kondo ,  Eiji Oue

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/337 ,  H01L21/768 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737 ,  H01L29/80

CPC classification number: H01L29/66916 ,  H01L21/8249 ,  H01L29/802

Abstract: The invention provides a bipolar transistor with improved performance. An insulation film comprising a silicon oxide film is formed by means of oxidation treatment on the side surface of an emitter aperture, and then an epitaxial layer comprised of SiGe is grown selectively in an aperture formed by removing a silicon nitride film so as to form under cut.

Abstract translation: 本发明提供了具有改进性能的双极晶体管。 通过在发射器孔径的侧表面上进行氧化处理形成包含氧化硅膜的绝缘膜，然后选择性地在由除去氮化硅膜形成的孔中生长由SiGe组成的外延层，以形成下面 切。

公开(公告)号：US06768192B2

公开(公告)日：2004-07-27

申请号：US10631793

申请日：2003-08-01

Applicant: Kumiko Takikawa ,  Satoshi Tanaka ,  Takashi Hashimoto ,  Yoshiyuki Okabe

Inventor： Kumiko Takikawa ,  Satoshi Tanaka ,  Takashi Hashimoto ,  Yoshiyuki Okabe

IPC: H01L2348

CPC classification number: H01L24/49 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.

Abstract translation: 一种防止低噪声放大器和接收混频器的频率特性劣化的引脚布局，包括在用于双频带发送/接收的半导体集成电路中，其中低噪声放大器的电路设置在距离 低端放大器封装外的引脚到焊盘最短; 两个低噪声放大器的接地引脚和高频信号引脚分别布置为不彼此相邻; 低噪声放大器的电源和接地引脚以及偏置电路的电源和接地引脚分别分开; 高频信号线不会相交。

公开(公告)号：US06630641B2

公开(公告)日：2003-10-07

申请号：US09848344

申请日：2001-05-04

Applicant: Taichiro Tamida ,  Takashi Hashimoto ,  Akihiro Suzuki ,  Akihiko Iwata ,  Atsushi Taneda

Inventor： Taichiro Tamida ,  Takashi Hashimoto ,  Akihiro Suzuki ,  Akihiko Iwata ,  Atsushi Taneda

IPC: B23H102

CPC classification number: B23H1/022 ,  B23H2300/20

Abstract: An electric discharge machining apparatus includes a wire electrode for machining a workpiece, and a first voltage applying unit for applying a voltage pulse. The voltage pulse has a rise time longer than a discharge formative time lag when a rectangular voltage pulse is applied, when a distance between the workpiece and the wire is an average value in machining, and rises to the same voltage as the rectangular voltage pulse.

Abstract translation: 放电加工装置包括用于加工工件的线电极和用于施加电压脉冲的第一施加电压单元。 当施加矩形电压脉冲时，当工件和线之间的距离是加工中的平均值时，电压脉冲具有比放电形成时滞更长的上升时间，并且上升到与矩形电压脉冲相同的电压。

公开(公告)号：US06629230B2

公开(公告)日：2003-09-30

申请号：US09871144

申请日：2001-05-30

Applicant: Takashi Hashimoto ,  Yasuo Kohashi

Inventor： Takashi Hashimoto ,  Yasuo Kohashi

IPC: G06F1200

CPC classification number: G06F13/387 ,  G06F13/1631 ,  Y02D10/14 ,  Y02D10/151

Abstract: In a host interface circuit performing data transmission/reception between an external host controller and a device connected to the external host controller, the external host controller generates, as external addresses to be supplied to the connected device, first addresses corresponding to the respective internal addresses in an internal storage space of the connected device, and a specific second address corresponding to internal addresses of a series of areas in the internal storage space; and the host interface circuit includes a first address conversion circuit for converting the first addresses into the internal addresses in the internal storage space, and a second address conversion circuit for converting the specific second address into the internal addresses in the internal storage space; and the specific second address is used when the external host controller makes continuous access to the serial areas in the internal storage space of the connected device. Therefore, the external host controller can make continuous access to a series of areas in the internal storage space of the connected device by using the specific address, without using DMA, between the external host controller and the host interface circuit. As the result, power consumption is reduced, and complexity in software processing is reduced.

公开(公告)号：US06603263B1

公开(公告)日：2003-08-05

申请号：US09688362

申请日：2000-10-12

Applicant: Takashi Hashimoto ,  Yasutaka Inanaga

Inventor： Takashi Hashimoto ,  Yasutaka Inanaga

IPC: H01J1100

CPC classification number: H01J11/38 ,  G09G3/294 ,  G09G3/2983 ,  H01J11/12 ,  H01J11/24 ,  H01J11/32 ,  H01J2211/245 ,  H01J2211/323 ,  H01J2211/365

Abstract: Column electrodes W1 to Wm are arranged on the side of a rear glass substrate along a first direction D1 at regular intervals. Row electrodes X1 to Xn and Y1 to Yn include (a) strip bus electrodes Xb1 to Xbn and Yb1 to Ybn alternately arranged on a surface of a front glass substrate closer to discharge spaces at regular pitches to extend in a second direction D2 and (b) square transparent electrodes Xt and Yt having ends connected to the bus electrodes Xb1 to Xbn and Yb1 to Ybn respectively. The transparent electrodes Xt and Yt alternately extend into single ones of unit areas AR adjacent to each other in the first direction D1 through the bus electrodes Xbi and Ybi connected with the ends thereof. The unit areas AR are separated into discharge cells C having discharge gaps defined by opposite edges of the transparent electrodes Xt and Yt and non-discharge cells NC having no discharge gaps. The discharge gaps C are not adjacent to each other in the first and second directions D1 and D2. Thus provided is an AC-PDP capable of suppressing/avoiding false discharge.

Abstract translation: 列电极W1〜Wm以规定间隔沿着第一方向D1布置在后玻璃基板侧。 行电极X1至Xn和Y1至Yn包括（a）交替布置在前玻璃基板的表面上的带状总线电极Xb1至Xbn和Yb1至Ybn，其更接近以规则间距排出的空间，以沿第二方向D2延伸，并且（b ）方形透明电极Xt和Yt，其端部分别连接到总线电极Xb1至Xbn和Yb1至Ybn。 透明电极Xt和Yt通过与其端部连接的总线电极Xbi和Ybi交替地延伸到在第一方向D1上彼此相邻的单个区域AR中的单个区域AR。 单元区域AR被分离成具有由透明电极Xt和Yt的相对边缘限定的放电间隙的放电单元C和不具有放电间隙的非放电单元NC。 放电间隙C在第一和第二方向D1和D2上彼此不相邻。 由此，能够抑制/避免假放电的AC-PDP。

公开(公告)号：US06576512B2

公开(公告)日：2003-06-10

申请号：US10251850

申请日：2002-09-23

Applicant: Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

Inventor： Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

IPC: H01L21336

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11546 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7835 ,  Y10S438/981

Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.

Abstract translation: 能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。 可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

公开(公告)号：US06576509B1

公开(公告)日：2003-06-10

申请号：US09639305

申请日：2000-08-16

Applicant: Shigeya Toyokawa ,  Takashi Hashimoto ,  Kenichi Kuroda ,  Shoji Yoshida ,  Toshiyuki Iwaki ,  Masamichi Matsuoka

Inventor： Shigeya Toyokawa ,  Takashi Hashimoto ,  Kenichi Kuroda ,  Shoji Yoshida ,  Toshiyuki Iwaki ,  Masamichi Matsuoka

IPC: H01L218242

CPC classification number: H01L27/10888 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

Abstract: In forming a plug 21 of a polycrystalline silicon film in a contact hole 19 to which a bit line BL is connected, the upper surface of the plug 21 is retracted downward from the upper edge of the contact hole 19, and a plug 22 of a laminate of a TiN film 26 and a W film 27 is formed on the plug 21. Then, the W film deposited on the contact hole 19 is patterned to form a bit line BL having a width narrower than the diameter of the contact hole 19. Here, the W film 27 constituting part of the plug 22 in the contact hole 19 is etched, but the TiN film 26 constituting another part of the plug 22 is not almost etched.

Abstract translation: 在连接有位线BL的接触孔19中形成多晶硅膜的插头21时，插头21的上表面从接触孔19的上边缘向下缩回，并且插头22 在插塞21上形成TiN膜26和W膜27的层压体。然后，将沉积在接触孔19上的W膜图案化，形成宽度比接触孔19的直径窄的位线BL。 这里，构成接触孔19中的插头22的一部分的W膜27被蚀刻，但构成插头22的另一部分的TiN膜26几乎不被蚀刻。

公开(公告)号：US06293770B1

公开(公告)日：2001-09-25

申请号：US09138669

申请日：1998-08-24

Applicant: Kazuhiko Matsumoto ,  Takashi Hashimoto ,  Taiki Aoyama

Inventor： Kazuhiko Matsumoto ,  Takashi Hashimoto ,  Taiki Aoyama

IPC: F04B1700

CPC classification number: F02M37/106 ,  B01D35/027 ,  F02M37/22 ,  F04D13/16

Abstract: A fuel tank cap body unit includes a fuel pump portion which is integrated with a fuel filter portion to form a filter-equipped pump. The filter-equipped pump is fixedly contained in a rotary tank having a flat base with which the base of the fuel tank is brought into contact. A fuel tank cap body through which a fuel discharge flow channel portion is passed, is provided. The fuel tank cap body includes a rotary-tank mounting wall, which can be made flexibly movable by a flexible mechanism, and can accommodate the rotary tank and the filter-equipped pump.

Abstract translation: 燃料箱盖体单元包括燃料泵部分，其与燃料过滤器部分成一体以形成配有过滤器的泵。 装有过滤器的泵固定地容纳在具有与基座接合的平坦基座的旋转罐中。 设置燃料排出流路部通过的燃料箱盖体。 燃料箱盖体包括旋转罐安装壁，其可以通过柔性机构灵活地移动，并且可以容纳旋转罐和装有过滤器的泵。