公开(公告)号：US5989759A

公开(公告)日：1999-11-23

申请号：US30886

申请日：1998-02-26

申请人： Atsushi Ando ,  Kazuyoshi Sugihara ,  Katsuya Okumura ,  Tetsuro Nakasugi

发明人： Atsushi Ando ,  Kazuyoshi Sugihara ,  Katsuya Okumura ,  Tetsuro Nakasugi

IPC分类号： G03F7/20 ,  H01J37/304 ,  H01J37/317 ,  H01L21/027 ,  G03F9/00

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F7/70675 ,  H01J37/3045 ,  H01J37/3174 ,  Y10S430/143

摘要： To achieve down-sizing and improvements of throughputs, light exposure and charge beam exposure are sometimes used together. In case of performing exposure of a desired pattern in a plurality of stages, a positional displacement of each of exposure patterns in the stages leads to a decrease in exposure accuracy. According to the present invention, in case of forming a fine pattern by exposure after exposure of a rough pattern, the exposure position of the rough pattern is adjusted, based on a latent image of the rough pattern which has been subjected to exposure. As a result, a positional displacement between rough and fine patterns is reduced so that a desired pattern can be formed with high accuracy.

摘要翻译： 为了实现规模缩小和吞吐量的提高，有时一起使用曝光和电荷束曝光。 在多级中进行期望图案的曝光的情况下，各级的曝光图案的位置偏移导致曝光精度降低。 根据本发明，在粗糙图案曝光后通过曝光形成精细图案的情况下，基于经受曝光的粗糙图案的潜像，调整粗糙图案的曝光位置。 结果，粗图案和精细图案之间的位置偏移减小，从而可以高精度地形成期望的图案。

公开(公告)号：US5950099A

公开(公告)日：1999-09-07

申请号：US629442

申请日：1996-04-09

申请人： Naohiro Shoda ,  Katsuya Okumura

发明人： Naohiro Shoda ,  Katsuya Okumura

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/52 ,  H01L21/265

CPC分类号： H01L21/28512

摘要： A method for fabricating a damascene interconnect includes the steps of depositing a metal layer of the surface of an insulating film; etching the metal layer and the insulating film to form an insulating groove; depositing a silicon layer on an upper surface on the metal layer and on each sidewall and a bottom of the insulating groove; annealing the silicon layer and the metal layer to form a silicide layer; implanting ions in the bottom of the insulating groove; and depositing an interconnect material in the insulating groove using selective chemical vapor deposition. In one embodiment, the metal layer is a titanium layer, the interconnect material is tungsten, and the implanted ions are arsenic ions.

摘要翻译： 一种用于制造镶嵌互连的方法包括沉积绝缘膜表面的金属层的步骤; 蚀刻金属层和绝缘膜以形成绝缘槽; 在金属层的上表面和绝缘槽的每个侧壁和底部上沉积硅层; 退火硅层和金属层以形成硅化物层; 将离子注入绝缘槽的底部; 以及使用选择性化学气相沉积在所述绝缘槽中沉积互连材料。 在一个实施例中，金属层是钛层，互连材料是钨，注入的离子是砷离子。

公开(公告)号：US5888876A

公开(公告)日：1999-03-30

申请号：US628094

申请日：1996-04-09

申请人： Jun-ichi Shiozawa ,  Yoshitaka Tsunashima ,  Katsuya Okumura

发明人： Jun-ichi Shiozawa ,  Yoshitaka Tsunashima ,  Katsuya Okumura

IPC分类号： H01L21/76 ,  H01L21/334 ,  H01L21/763 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L29/66181 ,  H01L21/763 ,  H01L21/76877

摘要： A method of filling one or more trenches formed in a silicon substrate includes the steps of forming a thin polycrystalline silicon film in a trench such that the thin polycrystalline silicon film is sufficiently thin so as to not close the trench; forming an amorphous silicon film on thin polycrystalline film and the surface of the substrate and in the trenches; and annealing the amorphous silicon film such that the amorphous silicon layer migrates to fill the trenches to a first level. The deposition and annealing steps are performed in ambient atmospheres having low partial pressures of H.sub.2 O and O.sub.2, the annealing temperature is higher than the deposition temperature, and the annealing pressure is greater than the deposition pressure.

摘要翻译： 填充形成在硅衬底中的一个或多个沟槽的方法包括以下步骤：在沟槽中形成薄多晶硅膜，使得薄多晶硅膜足够薄以便不关闭沟槽; 在薄多晶膜和衬底的表面和沟槽中形成非晶硅膜; 以及使所述非晶硅膜退火，使得所述非晶硅层迁移以将所述沟槽填充至第一水平。 沉积和退火步骤在具有低的H 2 O和O 2分压的环境气氛中进行，退火温度高于沉积温度，并且退火压力大于沉积压力。

公开(公告)号：US5849089A

公开(公告)日：1998-12-15

申请号：US818750

申请日：1997-03-14

申请人： Yoshitaka Tsunashima ,  Katsuya Okumura

发明人： Yoshitaka Tsunashima ,  Katsuya Okumura

IPC分类号： C23C16/44 ,  C23C16/40 ,  C23C16/448 ,  H01L21/205 ,  H01L21/31 ,  C23C16/00

CPC分类号： C23C16/4483 ,  C23C16/402 ,  C23C16/4485

摘要： Inside a first cylinder for structuring an evaporator, a second cylinder is provided. The second cylinder has an undulated surface and a plurality of fine holes are provided on this surface. A liquid TEOS is contained in a first space positioned between the first cylinder and the second cylinder, and a second space positioned inside the second cylinder is filled with a gas TEOS evaporated from the fine holes. The pressure of the gas TEOS is set to be almost equal to the pressure of the liquid TEOS.

摘要翻译： 在用于构造蒸发器的第一气缸内部，设置有第二气缸。 第二圆柱体具有波状表面，并且在该表面上设置有多个细孔。 液体TEOS容纳在位于第一气缸和第二气缸之间的第一空间中，并且位于第二气缸内部的第二空间填充有从细孔蒸发的气体TEOS。 气体TEOS的压力被设定为几乎等于液体TEOS的压力。

公开(公告)号：US5818217A

公开(公告)日：1998-10-06

申请号：US222392

申请日：1994-04-04

申请人： Fumio Komatsu ,  Katsuya Okumura ,  Motosuke Miyoshi

发明人： Fumio Komatsu ,  Katsuya Okumura ,  Motosuke Miyoshi

IPC分类号： G21K5/04 ,  H01J37/02 ,  H01J37/147 ,  H01J37/302 ,  H01L21/66 ,  G01R31/305

CPC分类号： H01J37/3026 ,  H01J37/026

摘要： To prevent electric charge up from being accumulated on the plane scanned by an electron beam and further to improve the S/N ratio, an electron beam irradiating apparatus comprising: position information signal outputting section for outputting position information signals, in sequence to designate positions at which an electron beam is irradiated on a plane scanned by the electron beam, so as to designate the irradiation positions at random; and irradiation controller for-controlling the electron beam to irradiate the electron beam at the irradiation positions in response to the outputted position information signals. Further, to integrate an photoelectric signal over a sufficient time interval within the period of the pixel clock signal, the electric signal detecting circuit comprises a plurality of sample hold circuits and a selecting circuit for selecting and activating the sample hold circuits in sequence.

摘要翻译： 为了防止电荷积累在由电子束扫描的平面上并进一步提高S / N比，电子束照射装置包括：位置信息信号输出部分，用于输出位置信息信号，以依次指定位置信息信号 电子束照射在由电子束扫描的平面上，以便随机地指定照射位置; 以及照射控制器，用于响应于输出的位置信息信号，控制电子束在照射位置照射电子束。 此外，为了在像素时钟信号的周期内在足够的时间间隔内积分光电信号，电信号检测电路包括多个采样保持电路和用于依次选择和激活采样保持电路的选择电路。

公开(公告)号：US5721173A

公开(公告)日：1998-02-24

申请号：US805314

申请日：1997-02-25

申请人： Hiroyuki Yano ,  Katsuya Okumura

发明人： Hiroyuki Yano ,  Katsuya Okumura

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76224 ,  H01L21/763

摘要： A method of forming a trench isolation structure is provided in which a film is formed on a semiconductor substrate and a trench is formed in the semiconductor substrate through the film. A dielectric material is deposited in the trench and on the film. An etch resistant film is formed on the portions of the dielectric material in the trench and on exposed portions of the film at edge regions of the trench. The dielectric material on the film is selectively removed and the etch resistant film remaining on the dielectric material in the trench is selectively removed.

摘要翻译： 提供一种形成沟槽隔离结构的方法，其中在半导体衬底上形成膜，并且通过膜在半导体衬底中形成沟槽。 电介质材料沉积在沟槽和膜上。 在沟槽中的介电材料的部分和沟槽的边缘区域的膜的暴露部分上形成耐蚀刻膜。 选择性地去除膜上的电介质材料，并且选择性地去除留在沟槽中的电介质材料上的耐蚀刻膜。

公开(公告)号：US5660744A

公开(公告)日：1997-08-26

申请号：US492322

申请日：1995-06-19

申请人： Makoto Sekine ,  Keiji Horioka ,  Haruo Okano ,  Katsuya Okumura ,  Isahiro Hasegawa ,  Masaki Narita

发明人： Makoto Sekine ,  Keiji Horioka ,  Haruo Okano ,  Katsuya Okumura ,  Isahiro Hasegawa ,  Masaki Narita

IPC分类号： H01J37/32 ,  B23K10/00

CPC分类号： H01J37/32623 ,  H01J37/3266

摘要： A surface processing apparatus comprises a container provided with a first electrode and a second electrode disposed opposite to the first electrode for supporting a substrate to be processed and filled with a gas at a reduced pressure, an electric field generator for generating an electric field between the first and second electrodes, and a magnetic field generator for generating a magnetic field in the vacuum container. The magnetic field generator comprises a plurality of magnet element groups arranged in a circle around the container so as to form a ring, each of the magnet element groups having an axis directed to a center of the circle and a synthetic magnetization direction and comprising one or a plurality of magnet elements having respective magnetization directions which are synthesized to be equal to the synthetic magnetization direction of the each of the magnetic element groups. One of the magnet element groups is so disposed that the synthetic magnetization direction thereof coincides with the axis thereof, and each of the magnet element groups other than the one magnet element group is so disposed that an angle of the synthetic magnetization direction thereof relative to the synthetic magnetization direction of the one magnet element group is substantially twice an angle of the axis thereof relative to the axis of the one magnet element group.

摘要翻译： 表面处理装置包括：容器，其设置有第一电极和与第一电极相对设置的第二电极，用于支撑待处理的基板并在减压下填充气体;电场发生器，用于在第一电极之间产生电场; 第一和第二电极以及用于在真空容器中产生磁场的磁场发生器。 磁场发生器包括围绕容器布置成圆形的多个磁体元件组，以便形成环，每个磁体元件组具有指向圆心的合成磁化方向的轴线，并包括一个或多个 多个磁体元件，其各自的磁化方向被合成为等于每个磁性元件组的合成磁化方向。 一个磁体元件组被设置成合成磁化方向与其轴线重合，并且除了一个磁体元件组之外的每个磁体元件组被设置成使得其合成磁化方向相对于 一个磁体元件组的合成磁化方向基本上是相对于一个磁体元件组的轴线的轴的两倍。

公开(公告)号：US5637153A

公开(公告)日：1997-06-10

申请号：US429159

申请日：1995-04-26

申请人： Reiji Niino ,  Yoshiyuki Fujita ,  Hideki Lee ,  Yasuo Imamura ,  Toshiharu Nishimura ,  Yuuichi Mikata ,  Shinji Miyazaki ,  Takahiko Moriya ,  Katsuya Okumura ,  Hitoshi Kato

发明人： Reiji Niino ,  Yoshiyuki Fujita ,  Hideki Lee ,  Yasuo Imamura ,  Toshiharu Nishimura ,  Yuuichi Mikata ,  Shinji Miyazaki ,  Takahiko Moriya ,  Katsuya Okumura ,  Hitoshi Kato

IPC分类号： C23C16/24 ,  C23C16/40 ,  C23C16/44 ,  B08B7/00 ,  B08B9/00

CPC分类号： C23C16/24 ,  C23C16/405 ,  C23C16/4405 ,  C23C16/4412

摘要： After a polysilicon film is formed on a wafer, a cleaning gas containing ClF.sub.3 at 10 to 50 vol % is supplied into a reaction tube and an exhaust pipe system at a flow rate of 3000 to 3500 SCCM, so as to remove a polysilicon-based film deposited on an inner wall surface of the reaction tube, the surface of a member incorporated in the reaction tube, and an inner wall surface of the exhaust pipe system while the film forming process, by etching using ClF.sub.3. The cleaning gas is supplied while the temperature in the reaction tube is maintained at 450.degree. C. or higher, and in a pressure condition set at the maintained temperature such that an etching rate of the polysilicon-based film by the cleaning gas is higher than an etching rate of silicon which is the material of the reaction tube or the member incorporated in the reaction tube.

摘要翻译： 在晶片上形成多晶硅膜之后，将含有10〜50体积％的ClF 3的清洗气体以3000〜3500SCCM的流量供给反应管和排气管系，以除去多晶硅 通过使用ClF 3的蚀刻，沉积在反应管的内壁表面上的薄膜，在反应管中结合的构件的表面和排气管系统的内壁表面。 在将反应管中的温度保持在450℃以上，在设定为维持温度的压力条件下，通过清洗气体使多晶硅系膜的蚀刻速度高于 作为反应管的材料或结合在反应管中的构件的硅的蚀刻速率。

公开(公告)号：US5611942A

公开(公告)日：1997-03-18

申请号：US397617

申请日：1995-03-02

申请人： Tadashi Mitsui ,  Katsuya Okumura

发明人： Tadashi Mitsui ,  Katsuya Okumura

IPC分类号： G01B21/30 ,  B81B1/00 ,  G01N37/00 ,  G01Q60/24 ,  G01Q70/10 ,  G01Q70/16 ,  H01J37/28 ,  H01J37/00 ,  B44C1/22

CPC分类号： G01Q60/38 ,  B82Y35/00 ,  Y10S438/978 ,  Y10S977/878

摘要： The present invention is a method for forming a three point atomic force microscope tip. The method includes forming a substantially longitudinally extending solid tip having a peripheral surface and a forward end surface. Three masks are formed by deposition of carbon upon the solid tip, with a first and second of the masks formed along the peripheral surface, and a third of the masks formed on the forward end surface. The mask covered tip is then etched for a predetermined period of time to remove material from both the tip and the mask. After the predetermined period of time has elapsed, the masks are completely removed, and the removal of material from the tip results in the formation of three spikes which are pointed to the location from which the masks were removed.

摘要翻译： 本发明是形成三点原子力显微镜尖端的方法。 该方法包括形成具有周边表面和前端表面的基本纵向延伸的固体尖端。 通过将碳沉积在固体末端上形成三个掩模，其中第一和第二掩模沿着外周表面形成，并且三分之一的掩模形成在前端表面上。 然后将掩模覆盖的尖端蚀刻预定时间段以从尖端和掩模两者中去除材料。 在经过预定时间之后，掩模被完全去除，并且从尖端去除材料导致三个尖峰的形成，这三个尖峰指向去除掩模的位置。

公开(公告)号：US5539179A

公开(公告)日：1996-07-23

申请号：US792592

申请日：1991-11-15

申请人： Toshihisa Nozawa ,  Junichi Arami ,  Shinji Kubota ,  Isahiro Hasegawa ,  Katsuya Okumura

发明人： Toshihisa Nozawa ,  Junichi Arami ,  Shinji Kubota ,  Isahiro Hasegawa ,  Katsuya Okumura

IPC分类号： B23Q3/15 ,  H01L21/683 ,  H02N13/00 ,  B23K10/00

CPC分类号： H02N13/00 ,  H01L21/6831 ,  H01L21/6833 ,  Y10T279/23

摘要： An electrostatic chuck for electrostatically holding a wafer is provided in a vacuum chamber formed in a magnetron plasma etching apparatus. The electrostatic chuck has a base member, a first insulating layer provided on the base member and made of polyimide, a second insulation layer made of AlN, a conductive sheet provided between first and second insulation layers, and an adhesive layer made of a thermosetting resin and adhering the first insulating layer to the second insulating layer. The wafer is placed on the second insulating layer, and power is supplied from a high voltage power supply to the conductive sheet via a feeding sheet, thereby creating static electricity and hence a coulombic force for holding the wafer on the second insulating layer.

摘要翻译： 用于静电保持晶片的静电卡盘设置在形成在磁控管等离子体蚀刻装置中的真空室中。 所述静电卡盘具有基材，在所述基材上设置的由聚酰亚胺构成的第一绝缘层，由AlN构成的第二绝缘层，设置在第一绝缘层和第二绝缘层之间的导电片，以及由热固性树脂 并且将第一绝缘层粘合到第二绝缘层。 将晶片放置在第二绝缘层上，并且通过馈电片从高压电源向导电片提供电力，从而产生静电，因此产生用于将晶片保持在第二绝缘层上的库仑力。