公开(公告)号：US20180138088A1

公开(公告)日：2018-05-17

申请号：US15871037

申请日：2018-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.

公开(公告)号：US20180012976A1

公开(公告)日：2018-01-11

申请号：US15695019

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.

公开(公告)号：US20170323852A1

公开(公告)日：2017-11-09

申请号：US15170954

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L23/535 ,  H01L29/267 ,  H01L29/24 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08 ,  H01L23/528 ,  H01L21/768 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming an epitaxial layer adjacent to the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a first contact hole in the ILD layer adjacent to the gate structure; and forming a cap layer in the recess, in which a top surface of the cap layer is even with or lower than a top surface of the substrate.

公开(公告)号：US20170323824A1

公开(公告)日：2017-11-09

申请号：US15643488

申请日：2017-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/2815 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/66719

Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

公开(公告)号：US09773887B2

公开(公告)日：2017-09-26

申请号：US14957623

申请日：2015-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chiao Wang ,  Chao-Hung Lin ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Li-Wei Feng ,  Yu-Hsiang Hung

IPC: H01L29/66 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/32 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first spacer around the gate structure, and a contact etch stop layer (CESL) adjacent to the first spacer; forming a cap layer on the gate structure, the first spacer, and the CESL; and removing part of the cap layer for forming a second spacer adjacent to the CESL.

公开(公告)号：US09755056B2

公开(公告)日：2017-09-05

申请号：US14607085

申请日：2015-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Chao-Hung Lin ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/665 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate having a transistor is provided, where the transistor includes a source/drain region. A dielectric layer is formed on the substrate, and a contact plug is formed in the dielectric layer to electrically connect the source/drain region. Next, a mask layer is formed on the dielectric layer, where the mask layer includes a first layer and a second layer stacked thereon. After this a slot-cut pattern is formed on the second layer of the mask layer, and a contact slot pattern is formed on the first layer of the mask layer. Finally, the second layer is removed and a contact opening is formed by using the contact slot pattern on the first layer.

公开(公告)号：US20170221834A1

公开(公告)日：2017-08-03

申请号：US15487396

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chiao Wang ,  Yu-Hsiang Hung ,  Chao-Hung Lin ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L23/544 ,  H01L21/28 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L23/544 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28132 ,  H01L21/32139 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.

公开(公告)号：US09691665B2

公开(公告)日：2017-06-27

申请号：US14825183

申请日：2015-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L23/535 ,  H01L27/088

CPC classification number: H01L21/823475 ,  H01L21/0206 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/0226 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.

公开(公告)号：US20170062615A1

公开(公告)日：2017-03-02

申请号：US14837781

申请日：2015-08-27

Applicant: United Microelectronics Corp.

Inventor： Ying-Chiao Wang ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Hon-Huei Liu ,  Yu-Hsiang Hung

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/24 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/24 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A first doped layer containing a first type of dopant is formed on the substrate only in the first area. A second doped layer containing a second type of dopant is formed on the substrate only in the second area. An annealing step is performed to drive the first type of dopant and the second type of dopant into the substrate.

Abstract translation: 公开了一种形成半导体器件的方法。 提供具有第一区域和第二区域的衬底。 含有第一种掺杂剂的第一掺杂层仅在第一区域中形成在衬底上。 仅在第二区域中在衬底上形成包含第二类掺杂剂的第二掺杂层。 执行退火步骤以将第一类型的掺杂剂和第二类型的掺杂剂驱动到衬底中。

公开(公告)号：US20170062349A1

公开(公告)日：2017-03-02

申请号：US14836947

申请日：2015-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chiao Wang ,  Yu-Hsiang Hung ,  Chao-Hung Lin ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L23/544 ,  H01L21/311 ,  H01L21/033 ,  H01L21/28

CPC classification number: H01L23/544 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28132 ,  H01L21/32139 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供了包括晶片和对准标记的半导体结构。 晶片具有切割区域，其包括中心区域，中间区域围绕中心区域，周边区域围绕中间区域。 对准标记设置在切割区域中，其中对准标记是镜像对称图案。 对准标记包括中间区域中的多个第二图案和设置在周边区域中的多个第三图案，其中每个第三图案包括多条线，并且该线的宽度比L的宽度小10倍 形状。 本发明还提供一种形成该方法的方法。