公开(公告)号：US20240155843A1

公开(公告)日：2024-05-09

申请号：US17994401

申请日：2022-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  CHIA CHING HSU ,  Shen-De Wang ,  Yung-Lin Tseng ,  WEICHANG LIU

IPC: H10B43/35 ,  H10B41/23 ,  H10B41/35 ,  H10B43/23

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/1158

Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

公开(公告)号：US20230099289A1

公开(公告)日：2023-03-30

申请号：US17502015

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHEN CHEN ,  Wei Cheng ,  KOK WUN TAN ,  Shen-De Wang

IPC: H01L27/1157 ,  H01L29/06 ,  H01L27/11524

Abstract: A semiconductor memory structure includes a substrate having a device cell region and a contact forming region in proximity to the device cell region. A memory cell transistor is disposed within the device cell region. The memory cell transistor includes a gate and a charge storage structure between the gate and the substrate. The gate includes an extended portion within the contact forming region. A first spacer is disposed on a sidewall of the gate within the device cell region. A second spacer is disposed on a sidewall of the extended portion of the gate within the contact forming region. The second spacer is higher than the first spacer.

公开(公告)号：US11127752B2

公开(公告)日：2021-09-21

申请号：US16798126

申请日：2020-02-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang ,  Chun-Sung Huang

IPC: H01L21/00 ,  H01L27/11573 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/792 ,  H01L21/765 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

公开(公告)号：US20210233924A1

公开(公告)日：2021-07-29

申请号：US17229848

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L27/11568 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092 ,  H01L29/49 ,  H01L21/027 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/3213 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

公开(公告)号：US10692875B2

公开(公告)日：2020-06-23

申请号：US16177812

申请日：2018-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Chun-Sung Huang ,  Yung-Lin Tseng ,  Wei-Chang Liu ,  Shen-De Wang

IPC: H01L27/115 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157

Abstract: A memory structure including a substrate, at least one stacked gate structure, a first spacer conductive layer, and a first contact is provided. The stacked gate structure is located on the substrate and includes a control gate. The control gate extends in a first direction. The first spacer conductive layer is located on one sidewall of the control gate and is electrically insulated from the control gate. The first spacer conductive layer includes a first merged spacer portion and a first non-merged spacer portion. A line width of the first merged spacer portion is greater than a line width of the first non-merged spacer portion. The first contact is connected to the first merged spacer portion. The memory structure can have a larger process window of contact.

公开(公告)号：US10153359B2

公开(公告)日：2018-12-11

申请号：US15234525

申请日：2016-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Shen-De Wang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11546

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second regions respectively. The first cell comprises a first dielectric layer, a floating gate electrode, an oxide-nitride-oxide (ONO) gate dielectric layer, a second dielectric layer, and a control gate electrode. The ONO gate dielectric layer is on the floating gate electrode in the first dielectric layer on the substrate. The control gate electrode is in both of the first dielectric layer and the second dielectric layer on the first dielectric layer. The ONO gate dielectric layer contacting with the control gate electrode is wholly below a top surface of the first dielectric layer.

公开(公告)号：US10020385B2

公开(公告)日：2018-07-10

申请号：US14220122

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Shan Chiu ,  Shen-De Wang ,  Zhen Chen ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  Jianjun Yang ,  Wei Ta

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L29/66833 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/792

Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.

公开(公告)号：US20180108837A1

公开(公告)日：2018-04-19

申请号：US15359975

申请日：2016-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146

Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.

公开(公告)号：US20180033961A1

公开(公告)日：2018-02-01

申请号：US15260754

申请日：2016-09-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode.

公开(公告)号：US09799705B1

公开(公告)日：2017-10-24

申请号：US15297164

申请日：2016-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen ,  Guoan Du

IPC: H01L45/00 ,  H01L27/24 ,  H01L21/768

CPC classification number: H01L27/2436 ,  H01L21/76877 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

Abstract: The present invention provides a semiconductor device. The semiconductor device includes a contact structure disposed in a first dielectric layer, a second dielectric layer disposed on the first dielectric layer and having an opening disposed therein, a spacer disposed in the opening and partially covering the contact structure, and a resistive random-access memory (RRAM) disposed on the contact structure and directly contacting the spacer, wherein the RRAM includes a bottom electrode, a top electrode, and a switching resistance layer disposed between the bottom electrode and the top electrode.