公开(公告)号：US06812536B2

公开(公告)日：2004-11-02

申请号：US10383753

申请日：2003-03-10

申请人： Shuichi Ueno ,  Yukio Nishida ,  Hiroshi Umeda ,  Kenichi Ohto ,  Takashi Terauchi ,  Shigeru Shiratake ,  Akinori Kinugasa

发明人： Shuichi Ueno ,  Yukio Nishida ,  Hiroshi Umeda ,  Kenichi Ohto ,  Takashi Terauchi ,  Shigeru Shiratake ,  Akinori Kinugasa

IPC分类号： H01L2976

CPC分类号： H01L29/42368 ,  H01L21/28247

摘要： A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.

摘要翻译： 作为栅极氧化膜的微笑氧化膜形成在由掺杂多晶硅层，钨层和SiON层构成的三层多金属栅极的下方。 微笑氧化膜具有位于多金属栅极的边缘下方的第一区域和位于多金属栅极的中心部分下方的第二区域。 第一区域的膜厚度大于第二区域的膜厚度。 与多晶硅层相比具有小的氧扩散速率的抗氧化膜完全覆盖多金属栅极而不暴露。

公开(公告)号：US06731535B1

公开(公告)日：2004-05-04

申请号：US10455523

申请日：2003-06-06

申请人： Tsukasa Ooishi ,  Shuichi Ueno ,  Shigehiro Kuge

发明人： Tsukasa Ooishi ,  Shuichi Ueno ,  Shigehiro Kuge

IPC分类号： G11C1114

CPC分类号： H01L27/224 ,  G11C11/16 ,  H01L27/228

摘要： A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.

摘要翻译： 非易失性半导体存储器件包括硅衬底，位线，字线和存储单元。 位线位于硅衬底的主表面上方，并且字线被提供以与位线相交。 存储单元位于位线和字线相交的区域，并且其一端电连接到位线，另一端电连接到字线。 存储单元包括串联电连接的TMR元件和存取二极管。 存取二极管包括n型硅层和通过熔融重结晶重结晶的p型硅层，并且在n型硅层和p型硅层之间的界面处具有pn结。 结果，可以廉价地制造尺寸减小并且具有高性能的非易失性半导体存储器件。

公开(公告)号：US06475844B1

公开(公告)日：2002-11-05

申请号：US09629485

申请日：2000-07-31

申请人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

发明人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L21/28518 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/4983 ,  H01L29/66659

摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

摘要翻译： 当扩散区域（7a）连接到位线并且扩散区域（8a）连接到栅极电极（3a）的远离存储节点的表面的一部分中时，形成硅化区域（11a） 存储节点。 在与位线连接的扩散区域（7a）的表面形成硅化区域（12a）。 提供一种MOSFET，其抑制从存储节点到栅电极的漏电流并且降低连接到位线的扩散区域的电阻和所述栅电极的电阻。

公开(公告)号：US06380036B1

公开(公告)日：2002-04-30

申请号：US09694003

申请日：2000-10-23

申请人： Hidekazu Oda ,  Shuichi Ueno ,  Takehisa Yamaguchi

发明人： Hidekazu Oda ,  Shuichi Ueno ,  Takehisa Yamaguchi

IPC分类号： H01L21336

CPC分类号： H01L21/26506 ,  H01L29/1033 ,  H01L29/105 ,  H01L29/66575

摘要： A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

摘要翻译： 在硅衬底的表面上形成硼扩散区。 在硼扩散区的表面形成一对n型源/漏区。 在位于成对的源/漏区之间的区域之间形成有栅极电极，其间具有栅极绝缘膜。 在位于成对的n型源极/漏极区之间的硅衬底的表面处形成氮注入区。 氮注入区域在硅衬底表面的深度不超过500的位置具有峰值氮浓度。 由此，可以获得容易小型化的晶体管结构。

公开(公告)号：US6017781A

公开(公告)日：2000-01-25

申请号：US755734

申请日：1996-11-25

申请人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

发明人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L27/1108 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S257/914

摘要： According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

摘要翻译： 根据制造薄膜晶体管（TFT）的方法，通过将硅或氮离子注入到多晶硅的区域中形成非晶硅，而位于栅电极的侧壁的区域选择性地使用步骤部分 栅电极。 然后，进行热处理以将非晶硅转化为多晶硅，剩余的多晶硅作为晶种。 结果，可以均匀地形成具有大晶粒尺寸的晶粒的多晶硅。 因此，可以提高TFT的电特性，并且每个TFT之间的电特性没有差异。

公开(公告)号：US07371882B2

公开(公告)日：2008-05-13

申请号：US10940652

申请日：2004-09-15

申请人： Shuichi Ueno ,  Takuji Shitara ,  Kenichi Nakamura ,  Fumisada Kosuge

发明人： Shuichi Ueno ,  Takuji Shitara ,  Kenichi Nakamura ,  Fumisada Kosuge

IPC分类号： C07C253/18

CPC分类号： F28D13/00 ,  B01J8/0055 ,  B01J8/1836 ,  B01J2208/00132 ,  B01J2208/00725 ,  C07C253/28 ,  C07C255/51

摘要： A reactor for producing a nitrile compound from a carbon ring or heterocyclic compound having organic substituents by a gas phase reaction using a fluidized catalyst bed with ammonia and a gas containing oxygen. In a cylindrical fluidized catalyst bed having a diameter of 2.0 meters or greater, partial vaporization-type cooling tubes (the cooling medium is partially vaporized in the tubes) and complete vaporization-type cooling tubes (the cooling medium is completely vaporized in the cooling tubes) are disposed in a specific arrangement. Water containing ionic SiO2 in 0.1 ppm or smaller and having an electric conductivity of 5 μS/cm or smaller is used as the cooling medium for the complete vaporization-type cooling tubes. The temperature of the reaction is easily stabilized and uniform distribution of temperature is obtained in the fluidized catalyst bed. Stable continuous operation is achieved for a long time in a commercial scale apparatus.

摘要翻译： 一种反应器，其由具有有机取代基的碳环或杂环化合物通过气相反应使用流化催化剂床与氨和含氧气体制备。 在直径为2.0米或更大的圆柱形流化催化剂床中，部分气化型冷却管（冷却介质在管中部分蒸发）和完全蒸发式冷却管（冷却介质在冷却管中完全汽化 ）以特定的布置处理。 使用0.1ppm以下的电导率为5μS/ cm以下的含有离子性SiO 2的水作为完全蒸发式冷却管的冷却介质。 反应的温度容易稳定，在流化催化剂床中得到均匀的温度分布。 在商业规模的设备中长期实现稳定的连续操作。

公开(公告)号：US06461934B2

公开(公告)日：2002-10-08

申请号：US09862311

申请日：2001-05-23

申请人： Yukio Nishida ,  Shuichi Ueno ,  Masashi Kitazawa

发明人： Yukio Nishida ,  Shuichi Ueno ,  Masashi Kitazawa

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. a The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b). After that, the surface is planarizedby depositing an insulating film in the unfilled space of the trench (103b).

摘要翻译： 通过简单的制造工艺形成不同深度的沟槽隔离区域，并且增加了半导体器件的可靠性。 在半导体衬底（101）上形成不同宽度的沟槽（103a，103b），在其上形成诸如氧化硅膜的底层膜（104）和诸如氮化硅膜的掩模材料（105）。 然后，在整个表面上沉积诸如氧化硅膜的绝缘膜，使得填充较窄的沟槽（103a）的程度。 此时，较宽的沟槽（103b）在其中央部分具有未填充的空间。 a然后将衬底（101）的表面垂直蚀刻回直到其暴露在沟槽103b中。 以沟槽（103a，103b）中的绝缘膜（106a，106b）作为掩模，垂直地各向异性地蚀刻衬底（101）的表面，以在沟槽（103b）中形成更深的底部（103c）。 之后，通过在沟槽（103b）的未填充空间中沉积绝缘膜来平坦化表面。

公开(公告)号：US06300664B1

公开(公告)日：2001-10-09

申请号：US08880508

申请日：1997-06-23

申请人： Takashi Kuroi ,  Shuichi Ueno ,  Hidekazu Oda ,  Satoshi Shimizu

发明人： Takashi Kuroi ,  Shuichi Ueno ,  Hidekazu Oda ,  Satoshi Shimizu

IPC分类号： H01L2976

CPC分类号： H01L29/0847 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66765 ,  H01L29/7833 ,  H01L29/78618

摘要： Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.

摘要翻译： 获得的是能够防止栅电极中所含杂质扩散的半导体器件及其制造方法。 在该半导体器件中，形成在P型硅衬底上的栅极氧化膜和P +型栅极掺杂有氮。

公开(公告)号：US6130463A

公开(公告)日：2000-10-10

申请号：US346999

申请日：1999-07-02

申请人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

发明人： Hidekazu Oda ,  Tomohiro Yamashita ,  Shuichi Ueno

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/49 ,  H01L21/441

CPC分类号： H01L27/10852 ,  H01L21/28518 ,  H01L27/10894 ,  H01L29/4983 ,  H01L29/66659 ,  H01L27/10873 ,  H01L27/10888

摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

公开(公告)号：US5600154A

公开(公告)日：1997-02-04

申请号：US546514

申请日：1995-10-20

申请人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

发明人： Satoshi Shimizu ,  Shuichi Ueno ,  Shigenobu Maeda ,  Takashi Ipposhi

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L27/108 ,  H01L29/12

CPC分类号： H01L27/1108 ,  H01L27/1281 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78675 ,  H01L29/78678 ,  Y10S257/914

摘要： According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

摘要翻译： 根据制造薄膜晶体管（TFT）的方法，通过将硅或氮离子注入到多晶硅的区域中形成非晶硅，而位于栅电极的侧壁的区域选择性地使用步骤部分 栅电极。 然后，进行热处理以将非晶硅转化为多晶硅，剩余的多晶硅作为晶种。 结果，可以均匀地形成具有大晶粒尺寸的晶粒的多晶硅。 因此，可以提高TFT的电特性，并且每个TFT之间的电特性没有差异。