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公开(公告)号：US11663075B2
公开(公告)日：2023-05-30
申请号：US17470584
申请日：2021-09-09
发明人： Scott E. Schaefer , Aaron P. Boehm
CPC分类号： G06F11/1048 , G06F11/0787 , G06F11/1068 , G11C7/1045 , G11C29/42 , G11C29/44
摘要： Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.
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公开(公告)号：US11645152B2
公开(公告)日：2023-05-09
申请号：US17734464
申请日：2022-05-02
申请人： Rambus Inc.
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/0625 , G06F3/0644 , G06F3/0673 , G06F11/1048
摘要： Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.
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公开(公告)号：US20190250984A1
公开(公告)日：2019-08-15
申请号：US15781063
申请日：2018-01-01
发明人： Yeye HE , Huang ZHIPENG
CPC分类号： G06F11/1024 , G06F11/00 , G06F11/10 , G06F11/1048 , G06F17/18 , G06F2201/81
摘要： Methods, computer systems, computer-storage media, and graphical user interfaces are provided for facilitating data error detection, according to embodiments of the present invention. In one embodiment, a target data set having a plurality of values for which to identify incompatible data is obtained. A pattern for each of the plurality of values is generated using at least one generalization language. A pair of patterns that represent a pair of values is utilized to identify a compatibility indicator that corresponds with a pair of training patterns in a compatibility index that match the pair of patterns. The compatibility indicator indicates the pair of patterns are incompatible with one another based on a statistical analysis performed in association with a corpus of data external to the target data set. An indication that the values are incompatible with one another is provided.
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公开(公告)号：US20190244676A1
公开(公告)日：2019-08-08
申请号：US16387846
申请日：2019-04-18
IPC分类号： G11C29/00 , G06F12/0871 , G06F12/1009 , G06F11/10
CPC分类号： G11C29/70 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1048 , G06F11/1064 , G06F12/0871 , G06F12/1009
摘要： Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.
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公开(公告)号：US20190220348A1
公开(公告)日：2019-07-18
申请号：US16127965
申请日：2018-09-11
发明人： Naoaki KOKUBUN , Masahiro KIYOOKA , Yoshiki NOTANI , Kenji SAKURADA , Daiki WATANABE , Hironori UCHIKAWA
CPC分类号： G06F11/1048 , G06F11/1044 , G06F11/1068 , G11C11/5642 , H03M13/1108 , H03M13/1111
摘要： According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value read from the non-volatile memory to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
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公开(公告)号：US20190196727A1
公开(公告)日：2019-06-27
申请号：US16289173
申请日：2019-02-28
申请人： SK hynix Inc.
发明人： Se-Hyun KIM
CPC分类号： G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/1048 , G11C16/107 , G11C16/26 , G11C16/3404 , G11C29/82
摘要： A memory system includes: a memory device including a plurality of memory blocks; and a controller suitable for selecting one or more first memory blocks based on a predetermined condition among the plurality of the memory blocks in a booting section, and increasing a read reclaim count value of one or more second memory blocks among the one or more first memory blocks for which a number of failed bits of read data exceeds a predetermined threshold.
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公开(公告)号：US20190164599A1
公开(公告)日：2019-05-30
申请号：US15822798
申请日：2017-11-27
发明人： David Avraham , Eran Sharon , Ran Zamir , Alexander Bazarsky
CPC分类号： G11C11/5642 , G06F11/1012 , G06F11/1048 , G11C7/14 , G11C16/28 , G11C29/021 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2207/2254 , G11C2211/5634
摘要： Read reference levels are used to distinguish different data states for information stored in non-volatile memory. A storage system recalibrates its read reference levels, to maintain accuracy of the read process, by sensing samples of data for different test read reference levels and using those samples to determine an improved set of read reference levels. At least a subset of the test read reference levels used for the samples are dynamically and adaptively chosen based on indications of error for previous samples.
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公开(公告)号：US20190122741A1
公开(公告)日：2019-04-25
申请号：US15793092
申请日：2017-10-25
CPC分类号： G11C16/3495 , G06F11/1048 , G11C11/56 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3445 , G11C2211/5641 , G11C2211/5644
摘要： Adaptively changing a fail bit count for an erase operation is disclosed. A memory system may detect an erase stuck bit condition in a group of memory cells. An erase stuck bit condition refers to a situation in which the threshold voltage of at least one memory cell on string tends to stick, such that the string cannot be erased. The memory system performs an action in response to detecting an erase stuck bit condition, in one embodiment. One possible action is to increase a fail bit count for erase operations for other groups of memory cells, which could also potentially suffer from erase bit stuck conditions. This can help reduce erase stress on groups of memory cells. It can also reduce the number of groups of memory cells that need to be retired for failing an erase operation.
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公开(公告)号：US20190121711A1
公开(公告)日：2019-04-25
申请号：US16222624
申请日：2018-12-17
申请人： SK hynix Inc.
发明人： Joon-Woo KIM
CPC分类号： G06F11/2094 , G06F11/1048 , G06F11/1068 , G06F12/0292 , G06F12/10 , G06F2201/805 , G06F2201/82 , G06F2212/1032 , G11C5/04 , G11C29/52 , G11C29/70
摘要： A memory module may include a first memory module comprising a plurality of first memory devices each having an extra memory region, a second memory module comprising a plurality of second memory devices each having an extra memory region, and a control logic suitable for writing/reading data to/from the first memory devices, wherein the control logic writes/reads target data to be transferred to/from a third memory device having an error among the first memory devices, to/from the extra memory regions of the second memory devices.
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公开(公告)号：US20190073261A1
公开(公告)日：2019-03-07
申请号：US16178528
申请日：2018-11-01
申请人： Intel Corporation
发明人： John B. HALBERT , Kuljit S. BAINS
CPC分类号： G06F11/1048 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1068 , G11C11/401 , G11C29/42 , G11C29/52 , H03M13/095 , H03M13/6566
摘要： An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.
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