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公开(公告)号:US20190243774A1
公开(公告)日:2019-08-08
申请号:US15993610
申请日:2018-05-31
发明人: Shih-Tien Liao , Yu-Hua Hsiao
IPC分类号: G06F12/10
CPC分类号: G06F12/10 , G06F2212/654
摘要: A memory management method and a storage controller using the same are provided. The memory management method includes: establishing an array; selecting a first block from spare blocks at an initial time point and storing a first index number of the first block to a look-ahead block; adding the first index number in the look-ahead block to the array at a first time point, selecting a second block from the spare blocks and replacing the first index number stored to the look-ahead block with a second index number of the second block, and programming the first block; and adding the second index number in the look-ahead block to the array at a second time point, selecting a third block from the spare blocks and replacing the second index number in the look-ahead block with a third index number of the third block, and programming the second block.
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公开(公告)号:US20190138219A1
公开(公告)日:2019-05-09
申请号:US15807949
申请日:2017-11-09
IPC分类号: G06F3/06 , G06F12/0862 , G06F12/1027 , G06F12/1009 , G06F12/02 , G06F12/0811
CPC分类号: G06F12/1027 , G06F3/0611 , G06F3/0659 , G06F3/0685 , G06F12/023 , G06F12/0253 , G06F12/0811 , G06F12/0862 , G06F12/1009 , G06F12/1036 , G06F2212/1016 , G06F2212/2542 , G06F2212/283 , G06F2212/602 , G06F2212/65 , G06F2212/651 , G06F2212/654 , G06F2212/657 , G06F2212/68 , G06F2212/681 , G06F2212/702
摘要: Processing within a computing environment is facilitated by ascertaining locality domain information of a unit of memory to processing capability within the computing environment. Once ascertained, the locality domain information of the unit of memory may be cached in a data structure to facilitate one or more subsequent lookups of the locality domain information associated with one or more affinity evaluations of the unit of memory to processing capability of the computing environment.
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公开(公告)号:US20180307607A1
公开(公告)日:2018-10-25
申请号:US15769348
申请日:2016-01-18
申请人: Hitachi, Ltd.
发明人: Katsuto SATO , Nobukazu KONDO , Naruki KURATA
IPC分类号: G06F12/0862 , G06F12/1009 , G06F12/109
CPC分类号: G06F12/0862 , G06F12/10 , G06F12/1009 , G06F12/109 , G06F2212/1016 , G06F2212/6026 , G06F2212/654
摘要: A computer system includes a main memory, a lower class memory, and a secondary storage medium and executes an operating system, an in-memory computing program, and a prefetch optimizer program. The in-memory computing program writes processing target data including a plurality of data objects stored in the secondary storage medium into a plurality of continuous areas on a virtual memory space and executes a process while accessing the continuous area. When detecting that the operating system executes a class-in process triggered upon a page fault for a predetermined virtual page, the prefetch optimizer program acquires information of the continuous area from the in-memory computing program and directs the operating system to execute a class-in process for virtual pages included in the predetermined continuous area including the predetermined virtual page.
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44.
公开(公告)号:US20180107591A1
公开(公告)日:2018-04-19
申请号:US15835419
申请日:2017-12-07
申请人: P4TENTS1, LLC
发明人: Michael S. Smith
CPC分类号: G06F12/0215 , G06F3/0613 , G06F3/065 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F12/0638 , G06F12/0866 , G06F12/12 , G06F2212/205 , G06F2212/654 , G06F2212/7203
摘要: An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, a second memory of a second memory class communicatively coupled to the first memory, and a third memory communicatively coupled hierarchically to the second memory. In operation, data is fetched using a time between an execution of a plurality of threads.
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公开(公告)号:US09912351B1
公开(公告)日:2018-03-06
申请号:US15673649
申请日:2017-08-10
发明人: Xiaoyang Li , Zongpu Qi , Zheng Wang , Mengchen Yang , Fangfang Wu , Shican Luo , Lei Meng , Jin Yu , Kuan-Jui Ho , Lin Li
CPC分类号: H03M7/3084 , G06F5/065 , G06F9/4498 , G06F12/0215 , G06F12/1018 , G06F17/30982 , G06F2212/401 , G06F2212/654 , H03M7/3086 , H03M7/6011 , H03M7/6017 , H03M7/6023
摘要: The invention introduces a method for accelerating hash-based compression, performed in a compression accelerator, comprising: receiving, by a plurality of hash functions, a plurality of substrings from an FSM (Finite-State Machine) in parallel; mapping, by each hash function, the received substring to a hash index and directing a selector to connect to one of a plurality of match paths according to the hash index; transmitting, by a matcher of each connected match path, a no-match message to the FSM when determining that a hash table does not contain the received substring; and transmitting, by the matcher of each connected match path, a match message and a match offset of the hash table to the FSM when determining that the hash table contains the received substring, wherein the match offset corresponds to the received substring.
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46.
公开(公告)号:US09824022B2
公开(公告)日:2017-11-21
申请号:US14485676
申请日:2014-09-13
发明人: Michael K. Gschwind
IPC分类号: G06F12/10 , G06F12/1027 , G06F12/1045
CPC分类号: G06F12/1027 , G06F12/1045 , G06F2212/654 , G06F2212/68
摘要: An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.
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47.
公开(公告)号:US09824021B2
公开(公告)日:2017-11-21
申请号:US14231669
申请日:2014-03-31
发明人: Michael K. Gschwind
IPC分类号: G06F12/10 , G06F12/1027 , G06F12/1045
CPC分类号: G06F12/1027 , G06F12/1045 , G06F2212/654 , G06F2212/68
摘要: An address translation capability in which information is obtained from an address translation structure to be used to translate a first address to a second address, the first address being of a first address type and the second address being of a second address type. The address translation structure includes a first set of information to translate the first address to one address of the second address type and a second set of information to translate the first address to another address of the second address type. To obtain the information, the first set of information or the second set of information is selected as the information to be used to translate the first address to the second address, based on an attribute of the first address.
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公开(公告)号:US09792215B2
公开(公告)日:2017-10-17
申请号:US14672133
申请日:2015-03-28
发明人: Jason Edward Podaima , Bohuslav Rychlik , Paul Christopher John Wiercienski , Kyle John Ernewein , Carlos Javier Moreira , Meghal Varia , Serag Gadelrab
IPC分类号: G06F12/12 , G06F12/0862 , G06F12/0875 , G06F12/10 , G06F12/1027
CPC分类号: G06F12/0862 , G06F12/0875 , G06F12/10 , G06F12/1027 , G06F2212/1021 , G06F2212/452 , G06F2212/602 , G06F2212/6028 , G06F2212/654 , G06F2212/684
摘要: Methods and systems for pre-fetching address translations in a memory management unit (MMU) of a device are disclosed. In an embodiment, the MMU receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the MMU.
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公开(公告)号:US09778869B2
公开(公告)日:2017-10-03
申请号:US15401765
申请日:2017-01-09
IPC分类号: G06F12/00 , G06F3/06 , G06F11/07 , G06F12/109
CPC分类号: G06F3/0622 , G06F3/0637 , G06F3/0673 , G06F11/0712 , G06F11/0727 , G06F11/073 , G06F11/0751 , G06F11/079 , G06F11/0793 , G06F12/1009 , G06F12/109 , G06F12/1408 , G06F12/145 , G06F12/1458 , G06F12/1475 , G06F12/1483 , G06F12/1491 , G06F2212/151 , G06F2212/654 , G06F2212/657
摘要: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.
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公开(公告)号:US09697136B2
公开(公告)日:2017-07-04
申请号:US14494000
申请日:2014-09-23
申请人: ARM Limited
发明人: Ali Ghassan Saidi , Anirruddha Nagendran Udipi , Matthew Lucien Evans , Geoffrey Blake , Robert Gwilym Dimond
IPC分类号: G06F12/1027
CPC分类号: G06F12/1027 , G06F2212/654 , G06F2212/681
摘要: A data processing system utilizing a descriptor ring to facilitate communication between one or more general purpose processors and one or more devices employs a system memory management unit for managing access by the devices to a main memory. The system memory management unit uses address translation data for translating memory addresses generated by the devices into addresses supplied to the main memory. Prefetching circuitry within the system memory management unit serves to detect pointers read from the descriptor ring and to prefetch address translation data into the translation lookaside buffer of the system memory management unit.
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