HIGH SPEED AND LOW OFFSET SENSE AMPLIFIER
    41.
    发明申请
    HIGH SPEED AND LOW OFFSET SENSE AMPLIFIER 审中-公开
    高速和低偏移感测放大器

    公开(公告)号:US20140355360A1

    公开(公告)日:2014-12-04

    申请号:US13906352

    申请日:2013-05-31

    发明人: Hsi-Wen Chen

    IPC分类号: G11C7/08 G11C7/06

    摘要: A sense amplifier includes a sensing circuit and an equalizing circuit. The sensing circuit is configured to supply one or more output signals according to one or more input signals. The equalizing circuit is configured to bring the sensing circuit to a metastable state from which the sensing circuit switches to an inverting state in response to a potential of the one or more input signals. Each transistor in the sensing circuit may switch to logic 0 or logic 1 faster and die-to-die PVT variations may be compensated, thereby providing high speed and low offset read operation.

    摘要翻译: 读出放大器包括感测电路和均衡电路。 感测电路被配置为根据一个或多个输入信号提供一个或多个输出信号。 均衡电路被配置为响应于一个或多个输入信号的电位使感测电路处于亚稳态,感测电路从该电路切换到反相状态。 感测电路中的每个晶体管可以更快地切换到逻辑0或逻辑1,并且可以补偿管芯到管芯PVT变化,从而提供高速度和低偏移读取操作。

    Switchable readout device
    43.
    发明授权
    Switchable readout device 有权
    可切换读出装置

    公开(公告)号:US08878595B2

    公开(公告)日:2014-11-04

    申请号:US13904538

    申请日:2013-05-29

    IPC分类号: H03K17/687 H03K17/00

    摘要: A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

    摘要翻译: 读出装置适用于双频带感测,并且包括放大器,分别连接到两个传感器的两个直接注入(DI)读出电路和开关模块。 通过开关模块的操作,DI读出电路之一可以与放大器电连接,并与另一个DI读出电路配合,以实现双频带感测功能。

    SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE
    44.
    发明申请
    SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE 有权
    SENSE放大器电路和半导体器件

    公开(公告)号:US20140293721A1

    公开(公告)日:2014-10-02

    申请号:US14306293

    申请日:2014-06-17

    IPC分类号: G11C11/4091

    摘要: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

    摘要翻译: 本发明的单端读出放大器电路包括第一和第二MOS晶体管以及第一和第二预充电电路。 第一MOS晶体管将位线驱动到预定电压并且切换位线和感测节点之间的连接,并且栅极连接到感测节点的第二MOS晶体管经由第一MOS晶体管放大信号。 第一预充电电路将位线预充电到第一电位,而第二预充电电路将感测节点预充电到第二电位。 在感测操作之前,当控制上述栅极电压降低时,位线被驱动到预定电压。 适当地设定预定电压,使得可以在电荷转移/分配模式之间的变化点附近获得在高电平和低电平之间的感测节点处的所需电压差。

    SIGNAL MARGIN CENTERING FOR SINGLE-ENDED eDRAM SENSE AMPLIFIER
    45.
    发明申请
    SIGNAL MARGIN CENTERING FOR SINGLE-ENDED eDRAM SENSE AMPLIFIER 有权
    用于单端eDRAM感应放大器的信号中心

    公开(公告)号:US20140293715A1

    公开(公告)日:2014-10-02

    申请号:US13851202

    申请日:2013-03-27

    IPC分类号: G11C11/4074

    摘要: Apparatus and methods for signal margin centering for single-ended eDRAM sense amplifier. A plurality of DRAM cells is connected to an input side of a multiplexer by a first bitline. A single-ended sense amplifier is connected to an output side of the multiplexer by a second bitline. The single-ended sense amplifier has a switch voltage. The second bitline is precharged to a selected voltage level. The multiplexer passes a signal voltage from a selected one of the plurality of DRAM cells to the second bitline. The selected voltage level is selected such that reception of the signal voltage of a first type adjusts a voltage of the second bitline in a first direction and reception of the signal voltage of a second type adjusts the voltage of the second bitline in a second direction opposite from the first direction, centering the signal voltage around the switch voltage.

    摘要翻译: 用于单端eDRAM读出放大器的信号容限定心的装置和方法。 多个DRAM单元通过第一位线连接到多路复用器的输入侧。 单端读出放大器通过第二位线连接到多路复用器的输出侧。 单端读出放大器具有开关电压。 第二位线被预充电到选定的电压电平。 复用器将来自多个DRAM单元中选定的一个的单元的信号电压传递到第二位线。 所选择的电压电平被选择为使得第一类型的信号电压的接收在第一方向上调节第二位线的电压,并且接收第二类型的信号电压在相反的第二方向上调节第二位线的电压 从第一个方向,围绕开关电压使信号电压居中。

    SWITCHABLE READOUT DEVICE
    47.
    发明申请
    SWITCHABLE READOUT DEVICE 有权
    可切换读取设备

    公开(公告)号:US20140197878A1

    公开(公告)日:2014-07-17

    申请号:US13904538

    申请日:2013-05-29

    IPC分类号: H03K17/00

    摘要: A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

    摘要翻译: 读出装置适用于双频带感测,并且包括放大器,分别连接到两个传感器的两个直接注入(DI)读出电路和一个开关模块。 通过开关模块的操作,DI读出电路之一可以与放大器电连接,并与另一个DI读出电路配合,以实现双频带感测功能。

    CIRCUIT AND METHOD FOR DYNAMICALLY CHANGING A TRIP POINT IN A SENSING INVERTER
    49.
    发明申请
    CIRCUIT AND METHOD FOR DYNAMICALLY CHANGING A TRIP POINT IN A SENSING INVERTER 有权
    用于动态改变传感逆变器中的三个点的电路和方法

    公开(公告)号:US20140126316A1

    公开(公告)日:2014-05-08

    申请号:US13671253

    申请日:2012-11-07

    申请人: LSI CORPORATION

    发明人: Rajiv Roy

    IPC分类号: H03L7/06 G11C7/02

    摘要: A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit associated with the base inverter circuit and configured to employ the previous logic-level voltage to decouple one of the logic-high and logic-low voltage sources from one of the inputs and thereby shift a trip voltage of the base inverter circuit toward the input voltage.

    摘要翻译: 用于动态地改变感测逆变器电路中的跳闸点电压的电路和方法。 在一个实施例中,感测反相器电路包括:(1)基本反相器电路,可在其相应输入端耦合到逻辑高电平和逻辑低电压源,并且被配置为将其输出从先前逻辑电平转换为当前逻辑 基于由基本反相器电路接收的输入电压的逻辑值的电压电压,以及(2)与基本反相器电路相关联并被配置为使用先前的逻辑电平电压来解耦逻辑高电平之一的反馈电路 和来自输入之一的逻辑低电压源,从而将基极逆变器电路的跳闸电压移向输入电压。

    Single-Ended Sense Amplifier for Solid-State Memories
    50.
    发明申请
    Single-Ended Sense Amplifier for Solid-State Memories 有权
    用于固态存储器的单端感测放大器

    公开(公告)号:US20140119093A1

    公开(公告)日:2014-05-01

    申请号:US13661250

    申请日:2012-10-26

    申请人: LSI CORPORATION

    IPC分类号: G11C7/06 G11C17/12 G11C7/12

    摘要: Described embodiments provide a memory having at least one sense amplifier. The sense amplifier has a first capacitor, an inverting amplifier, a switch, an amplifier, and a second capacitor. The first capacitor is coupled between the input of the sense amplifier and a first node. The inverting amplifier has an input coupled to the first node and an output coupled to an internal node and the switch is coupled between the input and output of the inverting amplifier. The amplifier has an input coupled to the internal node and an output coupled to an output of the sense amplifier and the second capacitor is coupled between the internal node and a control node. When data is to be read from the memory, the second capacitor forces a small voltage reduction onto the intermediate node, helping the sense amplifier resolve the data value stored in the memory cell.

    摘要翻译: 所描述的实施例提供具有至少一个读出放大器的存储器。 读出放大器具有第一电容器,反相放大器,开关,放大器和第二电容器。 第一电容器耦合在感测放大器的输入端和第一节点之间。 反相放大器具有耦合到第一节点的输入和耦合到内部节点的输出,并且开关耦合在反相放大器的输入和输出之间。 放大器具有耦合到内部节点的输入和耦合到读出放大器的输出的输出,第二电容耦合在内部节点和控制节点之间。 当要从存储器读取数据时,第二电容器迫使中间节点上的电压降低,帮助读出放大器解析存储在存储单元中的数据值。