公开(公告)号：US09755597B2

公开(公告)日：2017-09-05

申请号：US14971359

申请日：2015-12-16

Applicant: STMicroelectronics, Inc.

Inventor： Davy Choi

IPC: H03F3/45 ,  H03G3/02 ,  H03G1/00 ,  H03F1/02 ,  H03F1/26 ,  H03F3/30 ,  H03F3/393 ,  H03G1/02 ,  H03G3/30 ,  H03M1/18

CPC classification number: H03G3/02 ,  H03F1/0205 ,  H03F1/26 ,  H03F3/3022 ,  H03F3/393 ,  H03F3/45 ,  H03F3/45094 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45336 ,  H03G1/0035 ,  H03G1/02 ,  H03G3/3036 ,  H03M1/18

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

公开(公告)号：US09747246B2

公开(公告)日：2017-08-29

申请号：US14625196

申请日：2015-02-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Brian Deng

IPC: H05K7/10 ,  G06F13/42 ,  G06F13/362

CPC classification number: G06F13/4282 ,  G06F13/362 ,  Y02D10/14 ,  Y02D10/151

Abstract: An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.

公开(公告)号：US20170244539A1

公开(公告)日：2017-08-24

申请号：US15049296

申请日：2016-02-22

Applicant: STMicroelectronics, Inc.

Inventor： Charaf Hanna ,  Benjamin Nelson Darby ,  Zhifang J. Ni ,  John Wrobbel

IPC: H04L7/00

CPC classification number: H04L12/40052

Abstract: Upstream burst transmit times are dynamically communicated to the transmit unit in grants issued over time and in any order. A critical parameter is when to trigger the operation to order the buffered data stream for transmission. If the ordering operation is triggered too soon, a later grant of an earlier burst transmit time may not be accounted for and the subsequent transmission could violate the transmission order rule. If the ordering operation is triggered too late, the decision to transmit a burst at an earlier burst transmit time may violate the margin rule. To address these concerns, a fetch offset time in advance of each granted burst transmit time is assigned. As each fetch offset time is sequentially reached, a next partial data portion of the buffered data stream is prepared for burst communication.

公开(公告)号：US20170229391A1

公开(公告)日：2017-08-10

申请号：US15499665

申请日：2017-04-27

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. ZHANG

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0676 ,  H01L27/0682 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

公开(公告)号：US20170227569A1

公开(公告)日：2017-08-10

申请号：US15019453

申请日：2016-02-09

Applicant: STMicroelectronics, Inc.

Inventor： Milad Alwardi ,  Deyou Fang

IPC: G01P15/125 ,  G01P15/08

CPC classification number: G01P15/125 ,  G01C19/5776 ,  G01D5/2417 ,  G01R27/2605

Abstract: Disclosed herein is a device including a MEMS sensor configured to generate a first differential capacitance representing a change in capacitance from a first original sensing capacitance value and a second differential capacitance representing a change in capacitance from a second original sensing capacitance value, with the first and second original sensing capacitance values being mismatched. A compensation circuit is configured to generate outputs for compensating the first and second differential capacitances for the mismatch. A capacitance to voltage converter receives the first and second differential capacitances and the outputs of the compensation circuit as input and generates an output voltage as a function thereof.

公开(公告)号：US20170222018A1

公开(公告)日：2017-08-03

申请号：US15485754

申请日：2017-04-12

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

Abstract: An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

公开(公告)号：US20170219771A1

公开(公告)日：2017-08-03

申请号：US15491718

申请日：2017-04-19

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: G02B6/132 ,  G02B6/122 ,  G02B6/136

CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/1225 ,  G02B6/13 ,  G02B6/136 ,  G02B2006/121 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/14 ,  H01L23/522 ,  H01L23/53209 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.

公开(公告)号：US09707761B2

公开(公告)日：2017-07-18

申请号：US14523625

申请日：2014-10-24

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Dino Faralli ,  Michele Palmieri

IPC: B21D53/76 ,  B23P17/00 ,  B41J2/16 ,  B41J2/14

CPC classification number: B41J2/162 ,  B41J2/1433 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1626 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1632 ,  B41J2/1639 ,  B41J2/164 ,  B41J2/1642 ,  B41J2002/14475 ,  Y10T29/49401

Abstract: A nozzle plate for a fluid-ejection device, comprising: a first substrate made of semiconductor material, having a first side and a second side; a structural layer extending on the first side of the first substrate, the structural layer having a first side and a second side, the second side of the structural layer facing the first side of the first substrate; at least one first through hole, having an inner surface, extending through the structural layer, the first through hole having an inlet section corresponding to the first side of the structural layer and an outlet section corresponding to the second side of the structural layer; a narrowing element adjacent to the surface of the first through hole, and including a tapered portion such that the inlet section of the first through hole has an area larger than a respective area of the outlet section of the first through hole.

公开(公告)号：US20170194244A1

公开(公告)日：2017-07-06

申请号：US15464487

申请日：2017-03-21

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/535

Abstract: A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

公开(公告)号：US20170190175A1

公开(公告)日：2017-07-06

申请号：US15253618

申请日：2016-08-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Simon DODD

IPC: B41J2/14

CPC classification number: B41J2/14072 ,  B41J2/14201 ,  B41J2/1753 ,  B41J2/17553 ,  B41J2002/14362 ,  B41J2002/14491

Abstract: The present disclosure provides supports for a microfluidic die and one or more additional die including, but not limited to, microfluidic die, ASICs, MEMS devices, and sensors. This includes semi-flexible supports that allow a microfluidic die to be at a 90 degree angle with respect to another die and rigid supports that allow a microfluidic and another die to be in close proximity to each other.