公开(公告)号：US10128242B2

公开(公告)日：2018-11-13

申请号：US15804669

申请日：2017-11-06

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

Abstract: A substrate contact land for a first MOS transistor is produced in and on an active zone of a substrate of silicon on insulator type using a second MOS transistor without any PN junction that is also provided in the active zone. A contact land on at least one of a source or drain region of the second MOS transistor forms the substrate contact land.

公开(公告)号：US20180323821A1

公开(公告)日：2018-11-08

申请号：US15968927

申请日：2018-05-02

Applicant: STMicroelectronics SA

Inventor： Laurent CHABERT ,  Raphael PAULIN

IPC: H04B1/48 ,  H04B1/16 ,  H04B1/18 ,  H03F3/195 ,  H03F1/26

CPC classification number: H04B1/48 ,  H03F1/26 ,  H03F1/523 ,  H03F3/195 ,  H03F3/72 ,  H03F2200/06 ,  H03F2200/114 ,  H03F2200/181 ,  H03F2200/222 ,  H03F2200/231 ,  H03F2200/27 ,  H03F2200/294 ,  H03F2200/321 ,  H03F2200/396 ,  H03F2200/451 ,  H03F2200/489 ,  H03F2200/507 ,  H03F2200/519 ,  H03F2200/525 ,  H03F2200/61 ,  H03F2200/75 ,  H04B1/1615 ,  H04B1/18

Abstract: A communications device includes a transmission chain coupled to an antenna a receiver chain coupled to the antenna. The receiver chain includes an amplifier device having an input coupled to the antenna. A controlled switching circuit is included in the amplifier device and is operable to selectively disconnect conduction terminals of an amplifying transistor from power supply terminals when the transmission chain is operating to pass a transmit signal to the antenna.

公开(公告)号：US10096708B2

公开(公告)日：2018-10-09

申请号：US15230699

申请日：2016-08-08

Applicant: STMicroelectronics SA

Inventor： Sotirios Athanasiou ,  Philippe Galy

IPC: H01L29/78 ,  H01L27/12 ,  H01L23/528 ,  H01L21/84 ,  H01L29/66 ,  H01L21/74 ,  H01L29/786

Abstract: An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is delimited within the semiconductive film. A MOS transistor supported within the active zone includes a gate region situated above the active zone. The gate region includes a rectilinear part situated between source and drain regions. The gate region further includes a forked part extending from the rectilinear part. A raised semiconductive region situated above the active zone is positioned at least partly between portions of the forked part. A substrate contact for the transistor is electrically coupled to the raised semiconductive region.

公开(公告)号：US20180276526A1

公开(公告)日：2018-09-27

申请号：US15694510

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Thomas Bedecarrats

IPC: G06N3/04 ,  G06N3/063

CPC classification number: G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G11C11/54 ,  H01L27/027 ,  H01L27/0285 ,  H01L29/42376 ,  H03K3/356

Abstract: An integrated artificial neuron device includes an input signal node, an output signal node and a reference supply node. An integrator circuit receives and integrates an input signal to produce an integrated signal. A generator circuit receives the integrated signal and, when the integrated signal exceeds a threshold, delivers the output signal. The integrator circuit includes a main capacitor coupled between the input signal node and the reference supply node. The generator circuit includes a main MOS transistor coupled between the input signal node and the output signal node. The main MOS transistor has a gate that is coupled to the output signal node, and a substrate that is mutually coupled to the gate.

公开(公告)号：US20180254270A1

公开(公告)日：2018-09-06

申请号：US15694403

申请日：2017-09-01

Applicant: STMicroelectronics SA

Inventor： Johan Bourgeat

IPC: H01L27/02 ,  H01L27/06 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L27/0277 ,  H01L27/0629 ,  H01L28/20 ,  H02H9/046

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

公开(公告)号：US10050037B2

公开(公告)日：2018-08-14

申请号：US15609571

申请日：2017-05-31

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Florian Cacho ,  Vincent Huard

IPC: H03K3/01 ,  H01L27/092 ,  H03K3/037 ,  H03K19/21 ,  H01L29/10

Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.

公开(公告)号：US20180197848A1

公开(公告)日：2018-07-12

申请号：US15914387

申请日：2018-03-07

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Sotirios Athanasiou

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L27/0266 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/456

Abstract: An ESD protection device includes a MOS transistor connected between a first terminal and a second terminal and having a gate region, source/drain region and a well region electrically coupled by a resistive-capacitive circuit configured to control turn on of the MOS transistor in response to an ESD event. The resistive-capacitive circuit has a common part with at least one of the source, gate or drain regions of the MOS transistor and includes a capacitive element and a resistive element. A first electrode of the capacitive element is formed by the resistive element and a second electrode of the capacitive element is formed by at least a portion of a semiconductor film within which the source/drain region is formed.

公开(公告)号：US20180196289A1

公开(公告)日：2018-07-12

申请号：US15689167

申请日：2017-08-29

Applicant: STMicroelectronics SA

Inventor： Valerie Danelon ,  Denis Pache

IPC: G02F1/01 ,  G02F1/225 ,  G02F1/025 ,  G02F3/02 ,  G02B6/293 ,  H04B10/50

CPC classification number: G02F1/0123 ,  G02B6/293 ,  G02F1/025 ,  G02F1/2255 ,  G02F1/2257 ,  G02F3/026 ,  H04B10/50575

Abstract: A Mach-Zehnder modulator (MZM) includes a first optical path with a first diode coupled to a first voltage signal node and configured to modify a phase of a first light signal transmitted through the first optical path. A further diode is positioned in the first optical path and configured to introduce a phase shift to the first light signal. A second optical path includes a second diode coupled to a second voltage signal node and configured to modify a phase of a second light signal transmitted through the second optical path. A first voltage signal carried on the first voltage signal node and a second voltage signal carried on the second voltage signal node each vary between a reverse biasing voltage level and a forward biasing voltage level. An optical coupler is coupled the first and second optical paths.

公开(公告)号：US10014660B2

公开(公告)日：2018-07-03

申请号：US14827429

申请日：2015-08-17

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/125 ,  H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/343 ,  H01S5/022 ,  H01S5/042 ,  H01S5/10 ,  H01S5/187 ,  H01S5/323 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34

CPC classification number: H01S5/1237 ,  G02B6/30 ,  G02B6/34 ,  G02B2006/12061 ,  G02B2006/12121 ,  H01L2224/32 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02284 ,  H01S5/026 ,  H01S5/0421 ,  H01S5/1014 ,  H01S5/1032 ,  H01S5/1231 ,  H01S5/187 ,  H01S5/323 ,  H01S5/343 ,  H01S2301/166

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

公开(公告)号：US09998689B2

公开(公告)日：2018-06-12

申请号：US14557158

申请日：2014-12-01

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA

Inventor： David Coulon ,  Benoit Deschamps ,  Frederic Barbier

IPC: H01L21/00 ,  H04N5/345 ,  H01L27/146 ,  H04N5/378

CPC classification number: H04N5/345 ,  H01L27/14605 ,  H01L27/14647 ,  H01L27/14689 ,  H04N5/378

Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.