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公开(公告)号：US10297327B2
公开(公告)日：2019-05-21
申请号：US15952155
申请日：2018-04-12
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC: G11C16/26 , G11C16/14 , G11C16/08 , G11C7/06 , G11C8/08 , G11C16/10 , G11C16/28 , H01L27/112 , H01L27/11582 , H01L49/02
Abstract: The present invention relates to a flash memory system comprising one or more sense amplifiers for reading data stored in flash memory cells. The sense amplifiers utilize fully depleted silicon-on-insulator transistors to minimize leakage. The fully depleted silicon-on-insulator transistors comprise one or more fully depleted silicon-on-insulator NMOS transistors and/or one or more fully depleted silicon-on-insulator PMOS transistors.
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公开(公告)号：US20190121556A1
公开(公告)日：2019-04-25
申请号：US16228313
申请日：2018-12-20
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Vipin Tiwari , Nhan Do
IPC: G06F3/06 , G06F11/07 , G11C16/04 , H01L21/78 , H01L23/00 , H01L29/423 , G11C16/10 , H01L27/11521 , G11C16/26 , G11C16/08 , G11C16/34
Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.
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583.发明授权公开(公告)号：US10269432B2
公开(公告)日：2019-04-23
申请号：US15479235
申请日：2017-04-04
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Vipin Tiwari , Nhan Do
IPC: G11C16/06 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/34 , G11C16/26 , G11C16/04 , G11C16/10 , G11C16/28 , G11C16/32
Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.
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公开(公告)号：US20190114097A1
公开(公告)日：2019-04-18
申请号：US15784025
申请日：2017-10-13
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Vipin Tiwari , Nhan Do
IPC: G06F3/06 , G06F11/07 , G11C16/08 , G11C16/26 , G11C16/34 , G11C16/10 , H01L29/423 , H01L23/00 , H01L21/78 , G11C16/04 , H01L27/11521
Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.
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公开(公告)号：US10199109B2
公开(公告)日：2019-02-05
申请号：US15371496
申请日：2016-12-07
Applicant: Silicon Storage Technology, Inc.
Inventor： Xiaozhou Qian , Xiao Yan Pi , Kai Man Yue , Qing Rao , Lisa Bian
Abstract: Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.
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Patent Agency Ranking
公开(公告)号：US20180047454A1
公开(公告)日：2018-02-15
申请号：US15792590
申请日：2017-10-24
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen , Vipin Tiwari
CPC classification number: G11C16/28 , G11C7/062 , G11C7/067 , G11C7/12 , G11C16/00 , G11C16/06 , G11C16/24 , G11C16/26 , G11C2207/063 , H01L27/11519
Abstract: Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.
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公开(公告)号：US09892790B2
公开(公告)日：2018-02-13
申请号：US15249306
申请日：2016-08-26
Applicant: Silicon Storage Technology, Inc.
Inventor： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
IPC: G11C11/34 , G11C16/04 , G11C16/12 , H01L27/11517 , H01L27/11529 , H01L21/28 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/423 , H01L29/66 , H01L29/788 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34
CPC classification number: G11C16/0425 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C2216/18 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7887
Abstract: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
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公开(公告)号：US20170358360A1
公开(公告)日：2017-12-14
申请号：US15687191
申请日：2017-08-25
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
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公开(公告)号：US20170345840A1
公开(公告)日：2017-11-30
申请号：US15489548
申请日：2017-04-17
Applicant: Silicon Storage Technology, Inc.
Inventor： Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
IPC: H01L27/11568 , H01L21/306 , H01L21/3065 , H01L21/8238
CPC classification number: H01L27/11568 , H01L21/30604 , H01L21/30625 , H01L21/3065 , H01L21/823821 , H01L28/00
Abstract: A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.
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公开(公告)号：US20170345509A1
公开(公告)日：2017-11-30
申请号：US15163548
申请日：2016-05-24
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu
CPC classification number: G11C16/28 , G11C7/065 , G11C16/0433 , G11C16/14 , G11C16/24
Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the sensing amplifier includes a built-in voltage offset. In another embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors. In another embodiment, the sensing amplifier utilizes sloped timing for the reference signal to increase the margin by which a “0” or “1” are detected from the current drawn by the selected cell compared to the reference cell. In an another embodiment, a sensing amplifier is used without any voltage offset.
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