公开(公告)号：US08553165B2

公开(公告)日：2013-10-08

申请号：US13027247

申请日：2011-02-14

Applicant: Peng-Bo Xi ,  Yi-Jen Chen ,  Shin-Hung Yeh ,  Ya-Ling Hsu ,  Wei-Kai Huang

Inventor： Peng-Bo Xi ,  Yi-Jen Chen ,  Shin-Hung Yeh ,  Ya-Ling Hsu ,  Wei-Kai Huang

IPC: G02F1/1343 ,  G02F1/13 ,  G09G3/36 ,  G09G3/18 ,  G09G5/00 ,  G06F3/038 ,  H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L27/14 ,  H01L29/15 ,  H01L31/036

CPC classification number: G09G3/3648 ,  G02F1/136213 ,  G09G2320/0209

Abstract: A pixel structure includes a plurality of data lines and a common line. The common line overlaps each data line, and is coupled with each data line to respectively form a first coupling capacitor, a second coupling capacitor, a third coupling capacitor, a fourth coupling capacitor, a fifth coupling capacitor, and a sixth coupling capacitor. The third coupling capacitor is smaller than the second coupling capacitor, and the fifth coupling capacitor is smaller than the fourth coupling capacitor.

Abstract translation: 像素结构包括多条数据线和公共线。 公共线与每个数据线重叠，并且与每个数据线耦合以分别形成第一耦合电容器，第二耦合电容器，第三耦合电容器，第四耦合电容器，第五耦合电容器和第六耦合电容器。 第三耦合电容器小于第二耦合电容器，并且第五耦合电容器小于第四耦合电容器。

公开(公告)号：US20130260573A1

公开(公告)日：2013-10-03

申请号：US13437075

申请日：2012-04-02

Applicant: Hsin-Chang Lee ,  Yun-Yue Lin ,  Hung-Chang Hsieh ,  Chia-Jen Chen ,  Yih-Chen Su ,  Ta-Cheng Lien ,  Anthony Yen

Inventor： Hsin-Chang Lee ,  Yun-Yue Lin ,  Hung-Chang Hsieh ,  Chia-Jen Chen ,  Yih-Chen Su ,  Ta-Cheng Lien ,  Anthony Yen

IPC: H01L21/033

CPC classification number: G03F1/76

Abstract: A method of making a lithography mask with a stress-relief treatment is disclosed. The method includes providing a substrate and depositing an opaque layer on the substrate. The opaque layer is patterned to form a patterned mask. A stress-relief treatment is applied to the patterned mask by using an radiation exposure.

Abstract translation: 公开了一种制造具有应力消除处理的光刻掩模的方法。 该方法包括提供衬底并在衬底上沉积不透明层。 将不透明层图案化以形成图案化掩模。 通过使用辐射照射对图案化掩模施加应力消除处理。

公开(公告)号：US08546366B2

公开(公告)日：2013-10-01

申请号：US13483620

申请日：2012-05-30

Applicant: Yu-Jen Chen ,  Cheng-Jen Chou ,  Tun-Tschu Chang

Inventor： Yu-Jen Chen ,  Cheng-Jen Chou ,  Tun-Tschu Chang

IPC: A61K31/56 ,  A61K38/00 ,  A61P35/00

CPC classification number: A61K31/575

Abstract: In this patent, we isolated a novel compound from fruiting body of Antrodia cinnamomea, namely, (22R)-5α-lanosta-8,24-dien-3β,15α,21-triol. This compound possesses preferential cytotoxicity against human leukemia, pancreatic cancer, esophageal cancer, hepatoma, and cervical cancer cells.

Abstract translation: 在这项专利中，我们从番茄子实体中分离出一种新的化合物，即（22R）-5α-羊毛甾-8,24-二烯-3β，15α，21-三醇。 该化合物对人白血病，胰腺癌，食管癌，肝癌和宫颈癌细胞具有优先的细胞毒性。

公开(公告)号：US08536852B2

公开(公告)日：2013-09-17

申请号：US12730225

申请日：2010-03-23

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho

IPC: G05F3/30

CPC classification number: G06F1/26 ,  Y10T307/414 ,  Y10T307/549

Abstract: A current balance circuit includes a first and a second current sensors, an averager, a first and a second control modules, and a first and a second rheostat elements. The first and second current sensors receive a first current and a second current from a power source respectively and convert the first and second currents into a first and a second voltages. The averager receives the first and second voltages and calculates to obtain an average voltage. The first and second control modules receive the first voltage, the second voltage, and the average voltage, to obtain a first and a second control signals, to control current conduction ability of the first and second rheostat elements, to make the first and second currents keep a dynamic balance.

Abstract translation: 电流平衡电路包括第一和第二电流传感器，平均器，第一和第二控制模块以及第一和第二变阻器元件。 第一和第二电流传感器分别接收来自电源的第一电流和第二电流，并将第一和第二电流转换成第一和第二电压。 平均器接收第一和第二电压并计算得到平均电压。 第一和第二控制模块接收第一电压，第二电压和平均电压，以获得第一和第二控制信号，以控制第一和第二变阻器元件的电流传导能力，以使第一和第二电流 保持动态平衡。

公开(公告)号：US20130221443A1

公开(公告)日：2013-08-29

申请号：US13407507

申请日：2012-02-28

Applicant: Yu Chao LIN ,  Chih-Tang PENG ,  Shun-Hui YANG ,  Ryan Chia-Jen CHEN ,  Chao-Cheng CHEN

Inventor： Yu Chao LIN ,  Chih-Tang PENG ,  Shun-Hui YANG ,  Ryan Chia-Jen CHEN ,  Chao-Cheng CHEN

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L21/3065 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.

Abstract translation: 本发明涉及鳍状场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括主表面的衬底; 多个第一沟槽，具有第一宽度并从所述衬底主表面向下延伸到第一高度，其中相邻第一沟槽之间的第一空间限定第一鳍片; 以及多个第二沟槽，其具有小于第一宽度的第二宽度并且从所述衬底主表面向下延伸到大于所述第一高度的第二高度，其中相邻第二沟槽之间的第二空间限定第二鳍片。

公开(公告)号：US20130219350A1

公开(公告)日：2013-08-22

申请号：US13398923

申请日：2012-02-17

Applicant: Hsin-Chang Lee ,  Chia-Jen Chen ,  Lee-Chih Yeh ,  Anthony Yen

Inventor： Hsin-Chang Lee ,  Chia-Jen Chen ,  Lee-Chih Yeh ,  Anthony Yen

IPC: G06F17/50

CPC classification number: G03F1/00 ,  G03F1/20 ,  G03F1/22 ,  G03F1/36 ,  G03F1/42 ,  G03F1/70 ,  G06F17/5081 ,  G06F19/00 ,  G21K5/00

Abstract: A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask design database corresponding to a mask and containing a die area with one or more dies and a frame area outside the die area. Fiducial features within the frame area are identified, and from the fiducial features, an idle frame area is identified. A reference mask design, which corresponds to a reference mask configured to be aligned with the mask, is used to determine a reference density for the idle frame area. The idle frame area of the mask design database is modified to correspond to the reference density. The modified mask design database is then available for further use including manufacturing the mask.

Abstract translation: 公开了一种通过使一组中的掩模之间的框区域中的掩模材料的密度同步来减少层重叠误差的方法。 一种示例性方法包括创建对应于掩模并且包含具有一个或多个管芯的管芯区域和管芯区域外部的框架区域的掩模设计数据库。 识别帧区域内的基准特征，并从基准特征中识别空闲帧区域。 使用对应于被配置为与掩模对准的参考掩模的参考掩模设计来确定空闲帧区域的参考密度。 修改掩模设计数据库的空闲帧区域以对应于参考密度。 然后，修改的掩模设计数据库可用于进一步使用，包括制造掩模。

公开(公告)号：US08516581B2

公开(公告)日：2013-08-20

申请号：US13323863

申请日：2011-12-13

Applicant: Fu-Hau Hsu ,  Shih-Jen Chen ,  Chien-Ting Kuo ,  Jain-Shing Wu ,  Chuan-Sheng Wang

Inventor： Fu-Hau Hsu ,  Shih-Jen Chen ,  Chien-Ting Kuo ,  Jain-Shing Wu ,  Chuan-Sheng Wang

IPC: G06F11/00 ,  G06F11/30 ,  H04L29/06

CPC classification number: H04L67/02 ,  H04L51/12 ,  H04L51/32 ,  H04L63/1483

Abstract: A phishing processing method includes: an information input web page comprising an information input interface, through which information is transmitted to an information receiving address, is received. Determine if the information input web page is a phishing web page. If it is determined that the information input web page is the phishing web page, fake input information is transmitted to the information receiving address. When information for verification is received from an information transmitting address, if the received information for verification is the fake input information is determined. If the received information for verification is the fake input information, it is determined that the information transmitting address is a malicious address.

Abstract translation: 网络钓鱼处理方法包括：接收信息输入网页，其包括信息输入接口，通过该信息输入接口向信息接收地址发送信息。 确定信息输入网页是否是网络钓鱼网页。 如果确定信息输入网页是网络钓鱼网页，则将假输入信息发送到信息接收地址。 当从信息发送地址接收到用于验证的信息时，如果所接收的用于验证的信息是假输入信息被确定。 如果接收到的用于验证的信息是假输入信息，则确定信息发送地址是恶意地址。

公开(公告)号：US20130204558A1

公开(公告)日：2013-08-08

申请号：US13596063

申请日：2012-08-28

Applicant: TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

Inventor： TSUNG-SHENG HUANG ,  CHUN-JEN CHEN ,  DUEN-YI HO ,  WEI-CHIEH CHOU

IPC: G06F19/00 ,  G01R21/06

CPC classification number: G06F17/5036 ,  G06F17/5063 ,  G06F2217/78

Abstract: A method for calculating efficiency of a power supply system includes: displaying a parameter selection interface on the display unit for selecting power supply parameters and transmission line parameters. Obtaining power supply parameters and transmission line parameters selected by the user via the parameter selection interface when determining the user has finished the selection. Determining a efficiency of a selected power supply of the power supply parameters according to the relationship table, and calculating a sum efficiency according to the obtained power supply parameters and the transmission line parameters and the efficiency of the selected power supply. And calculating a total efficiency of the power supply system according to each sum efficiency when determining that all of the power supplies of the power supply system have been selected.

Abstract translation: 一种用于计算电源系统的效率的方法包括：在显示单元上显示参数选择界面，用于选择电源参数和传输线参数。 当确定用户已经完成选择时，通过参数选择界面获取用户选择的电源参数和传输线参数。 根据关系表确定电源参数的选定电源的效率，并根据获得的电源参数和传输线参数以及所选择的电源的效率来计算总和效率。 并且当确定已经选择了电源系统的所有电源时，根据每个总效率来计算电力供应系统的总效率。

公开(公告)号：US20130202992A1

公开(公告)日：2013-08-08

申请号：US13369061

申请日：2012-02-08

Applicant: Chia-Jen Chen ,  Anthony Yen ,  Hsin-Chang Lee ,  Sheng-Chi Chin

Inventor： Chia-Jen Chen ,  Anthony Yen ,  Hsin-Chang Lee ,  Sheng-Chi Chin

IPC: G03F1/54 ,  G03F1/50

CPC classification number: G03F1/42 ,  G03F1/50 ,  G03F1/84

Abstract: Provided is a method for reducing phase defects on many different types of semiconductor mask blanks. The method includes receiving a semiconductor mask blank substrate, creating alignment marks on the surface of the substrate, performing an inspection of the surface of the substrate to locate a plurality of surface defects, and repairing the plurality of surface defects on the surface of the substrate. A semiconductor mask is also provided that includes a repaired substrate a multilayer stack comprising a plurality of molybdenum and silicon layers, a capping layer, an absorber layer, and in some instances a photoresist layer.

Abstract translation: 提供了一种用于减少许多不同类型的半导体掩模坯料上的相缺陷的方法。 该方法包括：接收半导体掩模空白基板，在基板的表面上产生对准标记，对基板的表面进行检查以定位多个表面缺陷，以及修复基板表面上的多个表面缺陷 。 还提供了一种半导体掩模，其包括修复的衬底，包括多个钼和硅层的多层叠层，覆盖层，吸收层，并且在一些情况下为光致抗蚀剂层。

公开(公告)号：US20130141061A1

公开(公告)日：2013-06-06

申请号：US13655401

申请日：2012-10-18

Applicant: YU-JEN CHEN ,  CHUN-YUAN TIEN ,  FAN-CHIN KUNG ,  CHUN-PO CHEN ,  CHIA-MING YEH

Inventor： YU-JEN CHEN ,  CHUN-YUAN TIEN ,  FAN-CHIN KUNG ,  CHUN-PO CHEN ,  CHIA-MING YEH

IPC: G05F1/10

CPC classification number: H02M1/32 ,  H02M3/1588 ,  Y02B70/1466

Abstract: A buck converter configured for converting a voltage output from a power supply to a load includes a first switch, a second switch, an inductor, three compensators and a control microchip. The first switch and the second switch are connected in series between two ends of the power supply. A first end of the inductor is connected to a node between the first switch and the second switch; a second end of the inductor serves as an output terminal connected to the load. The compensators are correspondingly connected to the first switch, the second switch and the inductor. The control microchip is electrically connected to the first and second switches and the node. The control microchip controls the first and second switches to turn on or off, and executes a current protective process when output current of the output terminal exceeds a current protective threshold of the load.

Abstract translation: 被配置为将从电源输出的电压转换为负载的降压转换器包括第一开关，第二开关，电感器，三个补偿器和控制微芯片。 第一开关和第二开关串联在电源的两端之间。 电感器的第一端连接到第一开关和第二开关之间的节点; 电感器的第二端用作连接到负载的输出端子。 补偿器相应地连接到第一开关，第二开关和电感器。 控制微芯片电连接到第一和第二开关和节点。 控制微芯片控制第一和第二开关导通或关断，并且当输出端子的输出电流超过负载的当前保护阈值时执行当前的保护处理。