公开(公告)号：US20060004998A1

公开(公告)日：2006-01-05

申请号：US10883519

申请日：2004-06-30

Applicant: Bratin Saha ,  Matthew Merten ,  Per Hammarlund

Inventor： Bratin Saha ,  Matthew Merten ,  Per Hammarlund

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842

Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

公开(公告)号：US20160019067A1

公开(公告)日：2016-01-21

申请号：US14866875

申请日：2015-09-26

Applicant: Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

Inventor： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

公开(公告)号：US20150278119A1

公开(公告)日：2015-10-01

申请号：US14227178

申请日：2014-03-27

Applicant: THIAM WAH LOH ,  PER HAMMARLUND ,  ANDREAS WASSERBAUER ,  SWEE CHONG PETER KUAN ,  ECKHARD DELFS ,  DEEPAK A. MATHAIKUTTY ,  STEPHEN J. ROBINSON ,  GAUTHAM N. CHINYA ,  PERRY H. WANG ,  CHEE WENG TAN ,  HONG WANG ,  REZA FORTAS

Inventor： THIAM WAH LOH ,  PER HAMMARLUND ,  ANDREAS WASSERBAUER ,  SWEE CHONG PETER KUAN ,  ECKHARD DELFS ,  DEEPAK A. MATHAIKUTTY ,  STEPHEN J. ROBINSON ,  GAUTHAM N. CHINYA ,  PERRY H. WANG ,  CHEE WENG TAN ,  HONG WANG ,  REZA FORTAS

IPC: G06F12/14 ,  G11C29/52 ,  G06F21/57 ,  G11C7/10

CPC classification number: G06F12/1408 ,  G06F12/1491 ,  G06F21/10 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/032 ,  Y02D10/13

Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

Abstract translation: 采用硬件辅助虚拟化实现安全视频输出路径的系统和方法。 一个示例处理系统包括：存储器; 共享互连 以及经由所述共享互连通信地耦合到所述存储器的处理核心，所述处理核心：初始化第一虚拟机和第二虚拟机; 响应于接收由所述第一虚拟机发起的存储器访问事务以访问存储器缓冲器，用所述第一虚拟机的标识符标记所述存储器访问事务; 并且响应于接收由所述第二虚拟机发起的数字内容解码器访问事务，用所述第二虚拟机的标识符标记所述数字解码器访问事务。

公开(公告)号：US20140258757A1

公开(公告)日：2014-09-11

申请号：US14286536

申请日：2014-05-23

Applicant: Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

Inventor： Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

IPC: G06F1/32

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3265 ,  G06F1/3268 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/461 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/154 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.

Abstract translation: 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。

公开(公告)号：US08386823B2

公开(公告)日：2013-02-26

申请号：US13436835

申请日：2012-03-30

Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

公开(公告)号：US08239659B2

公开(公告)日：2012-08-07

申请号：US11529850

申请日：2006-09-29

Applicant: Stephan Jourdan ,  Michael Fetterman ,  Michael Cornaby ,  Per Hammarlund ,  Ronak Signhal ,  Glenn Hinton

Inventor： Stephan Jourdan ,  Michael Fetterman ,  Michael Cornaby ,  Per Hammarlund ,  Ronak Signhal ,  Glenn Hinton

IPC: G06F15/00 ,  G06F15/76

CPC classification number: G06F9/3824 ,  G06F9/30036 ,  G06F15/8084

Abstract: Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.

Abstract translation: 提供矢量完成掩码（VCM）处理技术。 数据结构包括用于特定操作的每个操作数的掩码字段。 处理器尝试通过掩码字段在数据结构中标识的多个操作数来执行操作。 如果成功检索操作数以执行操作，则数据结构中的相应掩码字段将被清除。 如果任何字段在数据结构中保持设置，并且可以使用以前未被操作的操作数重新处理操作，则处理器可以重置。

公开(公告)号：US20110264866A1

公开(公告)日：2011-10-27

申请号：US13175928

申请日：2011-07-04

Applicant: Quinn A. Jacobson ,  Anne Weinberger Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham N. Chinya ,  Bratin Saba ,  Ali-Reza Adl-Tabatabai ,  Gad S. Sheaffer

Inventor： Quinn A. Jacobson ,  Anne Weinberger Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham N. Chinya ,  Bratin Saba ,  Ali-Reza Adl-Tabatabai ,  Gad S. Sheaffer

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F11/3471 ,  G06F11/3648 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/145 ,  G06F2201/865

Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

Abstract translation: 使用存储器属性将信息中继到程序或其他代理的技术。 更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。

公开(公告)号：US20110087867A1

公开(公告)日：2011-04-14

申请号：US12970040

申请日：2010-12-16

Applicant: Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

Inventor： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

IPC: G06F9/44

CPC classification number: G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

Abstract: A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

Abstract translation: 处理器可以包括地址监视器表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20110035555A1

公开(公告)日：2011-02-10

申请号：US12909774

申请日：2010-10-21

Applicant: Hong Wang ,  Perry H. Wang ,  Jeffery A. Brown ,  Per Hammarlund ,  George Z. Chrysos ,  Doron Orenstein ,  Steve Shih-wei Liao ,  John P. Shen

Inventor： Hong Wang ,  Perry H. Wang ,  Jeffery A. Brown ,  Per Hammarlund ,  George Z. Chrysos ,  Doron Orenstein ,  Steve Shih-wei Liao ,  John P. Shen

IPC: G06F12/08 ,  G06F9/44 ,  G06F12/00 ,  G06F9/312

CPC classification number: G06F9/3842 ,  G06F9/383 ,  G06F9/3851 ,  G06F12/0862

Abstract: Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.

Abstract translation: 提供了用于在芯片多处理器（CMP）中执行推测性数据预取的装置，系统和方法。 数据由在CMP的一个核心上运行的辅助线程预取，而主程序在CMP的另一个核心上同时运行。 由辅助线程预取的数据被提供给辅助核心。 对于一个实施例，由辅助线程预取的数据被推送到主核心。 它也可以也可以不被提供给辅助核心。 在将数据广播到亲和组的所有核心的过程中，可能会将预取数据推送到主核心。 对于至少另一个实施例，根据主核心的请求，从辅助核心的本地高速缓存提供由辅助线程预取的数据到主核心。

公开(公告)号：US07523465B2

公开(公告)日：2009-04-21

申请号：US10422528

申请日：2003-04-24

Applicant: Tor M. Aamodt ,  Hong Wang ,  John Shen ,  Per Hammarlund

Inventor： Tor M. Aamodt ,  Hong Wang ,  John Shen ,  Per Hammarlund

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00

CPC classification number: G06F9/4843 ,  G06F8/433 ,  G06F9/3009 ,  G06F9/3808 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3851

Abstract: Methods and an apparatus for generating a speculative helper thread for cache prefetch are disclosed. The disclosed techniques select spawn-target pairs based on profile data and a series of calculations. Helper threads are then generated to launch at the selected spawn points in order to prefetch software instructions (or data) for a single-threaded software application. The generated helper threads are then attached to the single-threaded software application to create a multi-threaded software application.

Abstract translation: 公开了用于生成用于高速缓存预取的推测式辅助线程的方法和装置。 所公开的技术基于轮廓数据和一系列计算来选择产卵目标对。 然后生成辅助线程以在所选择的生成点上启动，以便为单线程软件应用程序预取软件指令（或数据）。 生成的助手线程然后连接到单线程软件应用程序以创建多线程软件应用程序。