公开(公告)号：US20070224776A1

公开(公告)日：2007-09-27

申请号：US11385968

申请日：2006-03-21

申请人： Wen-Chih Chiou

发明人： Wen-Chih Chiou

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming three-dimensional (3D) integrated circuits includes providing a first wafer comprising a silicon layer on a top surface of the first wafer, providing a second wafer comprising a silicon oxide layer on a top surface of the second wafer, bonding the first and the second wafers by placing a top surface of the silicon oxide layer against a top surface of the silicon layer and applying a pressure, and forming vias electrically interconnecting integrated circuits in the first and second wafers. The bonding is preferably preformed using a low pressure. A CMP and a plasma treatment are preferably performed to substantially flatten the surface of the silicon oxide layer before bonding.

摘要翻译： 一种用于形成三维（3D）集成电路的方法包括在第一晶片的顶表面上提供包括硅层的第一晶片，在第二晶片的顶表面上提供包括氧化硅层的第二晶片， 通过将硅氧化物层的顶表面放置在硅层的顶表面上并施加压力，以及在第一和第二晶片中形成电互连集成电路的通孔，形成第一和第二晶片。 优选使用低压进行粘合。 优选进行CMP和等离子体处理，以在接合之前使氧化硅层的表面基本平坦化。

公开(公告)号：US07220677B2

公开(公告)日：2007-05-22

申请号：US11106120

申请日：2005-04-13

申请人： Lin-Ping Li ,  Yung-Cheng Lu ,  Wen-Chih Chiou ,  Chih-Hsien Lin

发明人： Lin-Ping Li ,  Yung-Cheng Lu ,  Wen-Chih Chiou ,  Chih-Hsien Lin

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L22/10 ,  G01R31/2831 ,  H01L21/76838 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a multi-level semiconductor device to eliminate conductive interconnect protrusions following a WAT test, the method including forming a first metallization layer; carrying out a wafer acceptance testing (WAT) process; and, then carrying out a chemical mechanical polish (CMP) on the metallization layer.

摘要翻译： 一种用于形成多级半导体器件以在WAT测试之后消除导电互连突起的方法，所述方法包括形成第一金属化层; 进行晶圆验收测试（WAT）工艺; 然后在金属化层上进行化学机械抛光（CMP）。

公开(公告)号：US07208331B2

公开(公告)日：2007-04-24

申请号：US10949037

申请日：2004-09-24

申请人： Jyu-Horng Shieh ,  Wen-Chih Chiou ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Hun-Jan Tao ,  Chia-Jen Chen

发明人： Jyu-Horng Shieh ,  Wen-Chih Chiou ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Hun-Jan Tao ,  Chia-Jen Chen

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H01L22/34

摘要： Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.

摘要翻译： 公开了关键尺寸或轮廓测量的方法和结构。 该方法提供其中具有周期性开口的基板。 在开口中形成材料层，基本上平坦化基底的表面。 将散射方法应用于具有临界尺寸（CD）或轮廓测量的材料层的基底。

公开(公告)号：US20060254927A1

公开(公告)日：2006-11-16

申请号：US11127361

申请日：2005-05-12

申请人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Cheng Chan

发明人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Cheng Chan

IPC分类号： B23H3/00

CPC分类号： B24B37/04 ,  B23H5/08 ,  B24B49/12 ,  H01L21/67288

摘要： A system for use in manufacturing semiconductor devices, is provided. The system includes an electrochemical processing tool and an image sensor. The electrochemical processing tool includes an electrode located at a central region of a platen. The electrode is adapted for contacting a wafer workpiece during certain processing of the wafer workpiece using the tool. At least part of the electrode is viewable from above the platen when the electrochemical processing tool is operably assembled. The image sensor is capable of capturing an image of the viewable part of the electrode. The image sensor is positioned above the platen. The image sensor is adapted to be aimed at the electrode when an image of the electrode is to be taken with the image sensor.

摘要翻译： 提供一种用于制造半导体器件的系统。 该系统包括电化学处理工具和图像传感器。 电化学处理工具包括位于压板的中心区域的电极。 电极适于在使用该工具的晶片工件的某些处理期间接触晶片工件。 当电化学加工工具可操作地组装时，电极的至少部分可从压板上方观察。 图像传感器能够捕获电极的可视部分的图像。 图像传感器位于压板上方。 当用图像传感器拍摄电极的图像时，图像传感器适于瞄准电极。

公开(公告)号：US20060079154A1

公开(公告)日：2006-04-13

申请号：US10964145

申请日：2004-10-12

申请人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： B24B7/30 ,  B24B1/00

CPC分类号： H01L21/3212 ,  B24B37/042

摘要： A chemical-mechanical polishing (CMP) process for the manufacturing of semiconductor devices is disclosed. The process includes removing a first portion of a first layer of interconnect materials using a first platen and a first slurry, removing a second portion of the first layer using a second platen and a second slurry, removing a first portion of a second layer of the interconnect materials using a second platen and a third slurry, and removing a second portion of the second layer using a third platen and a fourth slurry.

摘要翻译： 公开了用于制造半导体器件的化学机械抛光（CMP）工艺。 该方法包括使用第一压板和第一浆料去除第一层互连材料的第一部分，使用第二压板和第二浆料除去第一层的第二部分，去除第二层的第一部分 使用第二压板和第三浆料的互连材料，以及使用第三压板和第四浆料除去第二层的第二部分。

公开(公告)号：US06946397B2

公开(公告)日：2005-09-20

申请号：US10714985

申请日：2003-11-17

申请人： William Hong ,  Chia-Che Chung ,  Chi-Wei Chung ,  Wen-Chih Chiou ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： William Hong ,  Chia-Che Chung ,  Chi-Wei Chung ,  Wen-Chih Chiou ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： B24B1/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/02074 ,  H01L21/02065 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684

摘要： An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.

摘要翻译： 公开了作为CMP工艺流程的一部分的氧化物抛光工艺。 在第一抛光站抛光铜层并且在第二抛光站抛光扩散阻挡层之后，在第三抛光工位上的键序列是施加第一氧化物浆料和第一DI水冲洗，然后是第二抛光 氧化物浆液，然后用第二次DI水冲洗。 因此，缺陷计数从几千减少到小于100.另一个重要因素是能够更有效地除去颗粒的低下降力。 改进的氧化物抛光方法具有与单一氧化物抛光剂和DI水漂洗方法相同的生产量，并且可以在任何三种浆料铜CMP工艺流程中实施。

公开(公告)号：US06409587B1

公开(公告)日：2002-06-25

申请号：US09713827

申请日：2000-11-15

申请人： Tsu Shih ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Wen-Chih Chiou

发明人： Tsu Shih ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Wen-Chih Chiou

IPC分类号： B24D1100

CPC分类号： B24D11/08 ,  B24B21/04 ,  B24B37/24 ,  G06T9/007

摘要： A composite, dual-hardness polishing pad for use in a linear chemical mechanical polishing apparatus and a method for forming the pad are described. In the composite, dual-hardness polishing pad, a pad body is first provided which has a leading edge and a trailing edge for mounting to a linear belt immediately adjacent to a second polishing pad. The pad body is fabricated of a material that has a first hardness, the leading edge contacts an object being polished on the composite polishing pad before the trailing edge when the linear belt turns in a linear polishing process. The composite polishing pad further includes a buffer pad that is adhesively joined to the leading edge of the pad body for contacting the object that is being polished, the buffer pad may be fabricated of a material that has a second hardness which is at least 20% smaller than the first hardness such that impact on the object being polished is minimized during a linear polishing process. The present invention is further directed to a method for adhesively joining a buffer pad to a pad body of a polishing pad.

摘要翻译： 描述了用于线性化学机械抛光装置的复合双硬度抛光垫和用于形成垫的方法。 在复合材料双硬度抛光垫中，首先提供具有前缘和后缘的垫体，用于安装在紧邻第二抛光垫的线性带上。 垫体由具有第一硬度的材料制成，当线性带在线性抛光过程中转动时，前缘在后缘之前在复合抛光垫上接触待抛光的物体。 所述复合抛光垫还包括缓冲垫，所述缓冲垫粘合地连接到所述垫体的前缘以接触被抛光的物体，所述缓冲垫可以由具有至少20％的第二硬度的材料制成， 小于第一硬度，使得在线性抛光工艺期间对被抛光物体的冲击最小化。 本发明还涉及一种用于将缓冲垫粘合地结合到抛光垫的衬垫体的方法。

公开(公告)号：US5466311A

公开(公告)日：1995-11-14

申请号：US196012

申请日：1994-02-10

申请人： Chen-Ti Hu ,  Wen-Chih Chiou

发明人： Chen-Ti Hu ,  Wen-Chih Chiou

IPC分类号： B22F9/24 ,  C22C1/04 ,  B22F1/00 ,  B22F3/12

CPC分类号： C22C1/0491 ,  B22F9/24

摘要： A method of manufacturing an Ni--Al intermetallic compound matrix composite comprising steps of a) providing an aluminum powder, b) providing a reinforced material, c) providing a reducing solution containing a reducing agent and nickel ions to be reduced, d) adding the aluminum powder and the reinforced material into the reducing solution, and e) permitting the reducing agent to reduce the nickel ions to be respectively deposited on the aluminum powder and the reinforced material. Such method permits the Ni--Al, Ni--Al+B intermetallic compound matrix composite to be produced inexpensively/efficiently/fastly.

摘要翻译： 一种制造Ni-Al金属间化合物基质复合材料的方法，包括以下步骤：a）提供铝粉末，b）提供增强材料，c）提供含还原剂和还原镍离子的还原溶液，d） 铝粉和增强材料进入还原溶液中，e）允许还原剂还原镍离子以分别沉积在铝粉末和增强材料上。 这种方法允许廉价/有效/快速地生产Ni-Al，Ni-Al + B金属间化合物基质复合材料。

公开(公告)号：US09130024B2

公开(公告)日：2015-09-08

申请号：US13417917

申请日：2012-03-12

申请人： Wen-Chih Chiou ,  David Ding-Chung Lu

发明人： Wen-Chih Chiou ,  David Ding-Chung Lu

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L21/30604 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/09 ,  H01L24/48 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/031 ,  H01L2224/0331 ,  H01L2224/0355 ,  H01L2224/05553 ,  H01L2224/08113 ,  H01L2224/08135 ,  H01L2224/48091 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

摘要翻译： 公开了一种使用冗余接合导体结构在多个半导体芯片之间进行层间电连接的三维半导体器件。 第一芯片或其它半导体衬底在其上表面上形成第一有源区，并且第二芯片或其它半导体衬底在其上表面上形成第二有源区。 根据本发明，当第二芯片已经被安装在第一芯片上方面向上或向下时，第一有效区域通过至少一个冗余结合导体结构耦合到第二有源区域。 在一个实施例中，每个冗余接合导体结构包括至少一个贯穿第二芯片的至少一个通孔部分，以执行该功能。 另一方面，冗余接合导体结构向下延伸到顶层互连。 本发明还包括制造这种装置的方法。

公开(公告)号：US09006101B2

公开(公告)日：2015-04-14

申请号：US13601265

申请日：2012-08-31

申请人： Hsin-Yu Chen ,  Ku-Feng Yang ,  Tasi-Jung Wu ,  Lin-Chih Huang ,  Yuan-Hung Liu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

发明人： Hsin-Yu Chen ,  Ku-Feng Yang ,  Tasi-Jung Wu ,  Lin-Chih Huang ,  Yuan-Hung Liu ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/31

CPC分类号： H01L23/528 ,  H01L21/76807 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5384 ,  H01L27/0617 ,  H01L2221/1031 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/00

摘要： An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanar with a top surface of the first metal line.

摘要翻译： 一种装置包括形成在衬底的第一侧上的层间绝缘层，形成在层间介电层上的第一金属化层，其中第一金属化层包括形成在第一金属化层上的第一金属线和介电层，其中， 电介质层包括具有与第一金属线的顶表面共面的底表面的金属结构。