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    Method for enhancing adhesion between layers in BEOL fabrication
    3.
    发明授权
    Method for enhancing adhesion between layers in BEOL fabrication 有权
    增加BEOL制作中层间粘附性的方法

    公开(公告)号：US07897505B2

    公开(公告)日：2011-03-01

    申请号：US11727133

    申请日：2007-03-23

    申请人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

    发明人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

    IPC分类号： H01L21/4763 ,  H01L21/00

    CPC分类号： H01L21/31633 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

    摘要： A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

    摘要翻译： 一种新颖的方法，用于在半导体晶片衬底上的集成电路制造过程中，在金属互连的形成过程中，增强相邻电介质层之间的界面附着力，特别是在蚀刻停止层和具有低介电常数（k）的上覆电介质层之间。 该方法可以包括提供衬底，在衬底上提供蚀刻停止层，在蚀刻停止层上提供富氧介电预置层，并在富氧电介质预层上提供主要电介质层。 然后在电介质层中形成金属互连。 在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。

    Methods for improving uniformity of cap layers
    4.
    发明申请
    Methods for improving uniformity of cap layers 有权
    改善盖层均匀性的方法

    公开(公告)号：US20080032472A1

    公开(公告)日：2008-02-07

    申请号：US11524000

    申请日：2006-09-20

    申请人： Chen-Hua Yu ,  Ming-Shih Yeh ,  Chih-Hsien Lin ,  Yung-Cheng Lu ,  Hui-Lin Chang

    发明人： Chen-Hua Yu ,  Ming-Shih Yeh ,  Chih-Hsien Lin ,  Yung-Cheng Lu ,  Hui-Lin Chang

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/76849 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/76826

    摘要： A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.

    摘要翻译： 形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成金属化层，其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸 进入低k电介质层，对低k电介质层进行处理以形成亲水性顶表面，以及在溶液中的金属特征上镀覆盖层。

    Method for enhancing adhesion between layers
    5.
    发明申请
    Method for enhancing adhesion between layers 有权
    提高层间粘附性的方法

    公开(公告)号：US20080233765A1

    公开(公告)日：2008-09-25

    申请号：US11727133

    申请日：2007-03-23

    申请人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

    发明人： Chung-Chi Ko ,  Lih-Ping Li ,  Yung-Cheng Lu ,  Hui-Lin Chang ,  Chih-Hsien Lin

    IPC分类号： H01L21/469 ,  H01L21/31

    CPC分类号： H01L21/31633 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835

    摘要： A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.

    摘要翻译： 一种新颖的方法，用于在半导体晶片衬底上的集成电路制造过程中，在金属互连的形成过程中，增强相邻电介质层之间的界面附着力，特别是在蚀刻停止层和具有低介电常数（k）的上覆电介质层之间。 该方法可以包括提供衬底，在衬底上提供蚀刻停止层，在蚀刻停止层上提供富氧介电预置层，并在富氧电介质预层上提供主要电介质层。 然后在电介质层中形成金属互连。 在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。

    Delay-locked loop
    7.
    发明授权
    Delay-locked loop 有权
    延迟锁定环路

    公开(公告)号：US08368445B2

    公开(公告)日：2013-02-05

    申请号：US13174798

    申请日：2011-07-01

    申请人： Chih-Hsien Lin ,  Chih-Wei Mu ,  Ming-Shih Yu

    发明人： Chih-Hsien Lin ,  Chih-Wei Mu ,  Ming-Shih Yu

    IPC分类号： H03L7/06

    CPC分类号： H03L7/095 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/1075

    摘要： A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.

    摘要翻译： 提供接收参考时钟信号并输出​​输出时钟信号的延迟锁定环路（DLL）。 DLL包括相位检测器，延迟链，防伪锁（AFL）电路和环路滤波器。 相位检测器根据参考时钟信号和输出时钟信号之间的相位比较器输出第一比较信号。 延迟链通过延迟不同间隔的参考时钟信号来产生多个选通时钟信号和输出时钟信号。 AFL电路根据参考时钟信号和选通时钟信号之间的相位比较输出第二比较信号。 环路滤波器根据第一和第二比较信号控制输出时钟信号的延迟时间，以将输出时钟信号的延迟时间锁定在预设值。

    Fiber container and associated optical communication device
    9.
    发明授权
    Fiber container and associated optical communication device 失效
    光纤容器及相关光通讯装置

    公开(公告)号：US06873778B2

    公开(公告)日：2005-03-29

    申请号：US10291836

    申请日：2002-11-12

    申请人： Tsung-Yueh Tsai ,  Chin-Hsiang Wang ,  Yu-Ting Lee ,  Chih-Hsien Lin

    发明人： Tsung-Yueh Tsai ,  Chin-Hsiang Wang ,  Yu-Ting Lee ,  Chih-Hsien Lin

    IPC分类号： B65H18/08 ,  G02B6/00 ,  H01S3/067

    CPC分类号： H01S3/06704

    摘要： A fiber container receiving optical fibers has a body, a space defined in the body, a reel disposed inside the body, wherein a groove is defined around the periphery of the reel. The optical fibers are twisted around the reel and received in the groove. Furthermore, the fiber container is able to apply to the active/passive optical communication device, such as an erbium doped fiber amplifier (EDFA) or a dense wavelength division multiplexer (DWDM).

    摘要翻译： 容纳光纤的纤维容器具有主体，在主体中限定的空间，设置在主体内部的卷轴，其中围绕卷轴的周边限定有凹槽。 光纤绕卷轴扭转并被接收在槽中。 此外，光纤容器能够应用于有源/无源光通信设备，例如掺铒光纤放大器（EDFA）或密集波分复用器（DWDM）。

    Method of forming resistors
    10.
    发明授权
    Method of forming resistors 有权
    形成电阻的方法

    公开(公告)号：US06732422B1

    公开(公告)日：2004-05-11

    申请号：US10037811

    申请日：2002-01-04

    申请人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

    发明人： Kong-Beng Thei ,  Chih-Hsien Lin ,  Shyh-Chyi Wong

    IPC分类号： H01C1700

    CPC分类号： H01L28/20 ,  H01C7/006 ,  H01C17/0656 ,  H01C17/075 ,  H01L27/0802 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49098

    摘要： A method of forming a resistor is described which achieves improved resistor stability and voltage coefficient of resistance. A resistor is formed from a conducting material such as doped silicon or polysilicon. The resistor has a rectangular first, second, third, fourth, and fifth resistor elements. A layer of protective dielectric is formed over the first, second, and third resistor elements leaving the fourth and fifth resistor elements exposed. The conducting material in the exposed fourth and fifth resistor elements is then changed to a silicide to form low resistance contacts between the second and fourth resistor elements and between the second and fourth resistor elements. The second and third resistor elements are wider than the first resistor element and provide a low resistance contacts to the first resistor element. This provides a low voltage coefficient of resistance and thermal process stability for the resistor.

    摘要翻译： 描述形成电阻器的方法，其实现了电阻器稳定性和电阻的电压系数的改善。 电阻器由诸如掺杂硅或多晶硅的导电材料形成。 电阻器具有矩形的第一，第二，第三，第四和第五电阻元件。 在第一，第二和第三电阻器元件上形成保护电介质层，留下第四和第五电阻元件。 然后将暴露的第四和第五电阻器元件中的导电材料改变为硅化物以在第二和第四电阻器元件之间以及第二和第四电阻器元件之间形成低电阻触点。 第二和第三电阻器元件比第一电阻器元件宽，并且向第一电阻器元件提供低电阻触点。 这为电阻器提供了低电阻系数和热处理稳定性。