公开(公告)号：US08062946B2

公开(公告)日：2011-11-22

申请号：US11093847

申请日：2005-03-30

Applicant: Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/336

CPC classification number: H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/165 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

Abstract translation: 具有晶格失配区的应变通道晶体管结构及其制造方法。 晶体管结构包括具有应变沟道区的衬底，包括表面上具有第一自然晶格常数的第一半导体材料，覆盖在应变沟道区上的栅极电介质层，覆盖栅极电介质层的栅电极和源极 区域和漏极区域相邻地邻近应变通道区域，其中源区域和漏极区域中的一个或两个包括晶格失配区域，其包含具有不同于第一自然晶格常数的第二自然晶格常数的第二半导体材料。

公开(公告)号：US07834345B2

公开(公告)日：2010-11-16

申请号：US12205585

申请日：2008-09-05

Applicant: Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

Inventor： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC: H01L29/94

CPC classification number: H01L29/7391 ,  H01L21/26586

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract translation: 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

公开(公告)号：US07758716B2

公开(公告)日：2010-07-20

申请号：US11610642

申请日：2006-12-14

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: C23F1/00

CPC classification number: H05K3/068 ,  B05B1/205 ,  H05K2203/075 ,  Y10S134/902

Abstract: An apparatus (100) for spraying an etchant solution on a preformed printed circuit board (30) includes a number of feed pipes (40) for supplying the etchant solution and a number of nozzles (45) mounted on the feed pipes. Each of the feed pipes has a middle portion (402) and two end portions (401). The middle portions of the feed pipes are located on a first plane and the end portions of the feed pipes are located on a second plane parallel to the first plane. The number of nozzles are mounted on the middle portion and the two end portions of each feed pipe. The number of nozzles are in fluid communication with the feed pipes.

Abstract translation: 用于在预成型印刷电路板（30）上喷涂蚀刻剂溶液的设备（100）包括用于供应蚀刻剂溶液的多个供给管（40）和安装在进料管上的多个喷嘴（45）。 每个进料管具有中间部分（402）和两个端部（401）。 进料管的中间部分位于第一平面上，并且进料管的端部位于平行于第一平面的第二平面上。 喷嘴的数量安装在每个进料管的中间部分和两个端部。 喷嘴的数量与进料管流体连通。

公开(公告)号：US20100167485A1

公开(公告)日：2010-07-01

申请号：US12722247

申请日：2010-03-11

Applicant: Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L21/336 ,  H01L21/3205

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/76844 ,  H01L21/7685 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅极电介质相邻的源极/漏极区域; 源/漏区上的硅化物区; 硅化物区域的顶部和物理接触处的金属层; 金属层上的层间电介质（ILD）; 和ILD的接触开口。 金属层通过接触开口露出。 金属层进一步在ILD下延伸。 半导体结构还包括接触开口中的接触。

公开(公告)号：US20100167101A1

公开(公告)日：2010-07-01

申请号：US12546004

申请日：2009-08-24

Applicant: Tsung-Hsiung Wang ,  Jing-Pin Pan ,  Wen-Chin Lee ,  Yueh-Wei Lin ,  Ya-Tin Hsu ,  Chung-Liang Chang ,  Chih-Jer Shih

Inventor： Tsung-Hsiung Wang ,  Jing-Pin Pan ,  Wen-Chin Lee ,  Yueh-Wei Lin ,  Ya-Tin Hsu ,  Chung-Liang Chang ,  Chih-Jer Shih

IPC: H01M8/10

CPC classification number: H01M8/1041 ,  C08G73/12 ,  C08J5/2256 ,  C08J2371/12 ,  C08J2400/202 ,  C08L79/085 ,  H01M4/92 ,  H01M8/1023 ,  H01M8/1025 ,  H01M8/1027 ,  H01M8/103 ,  H01M8/1032 ,  H01M8/1048 ,  Y02E60/521

Abstract: Proton exchange membrane compositions having high proton conductivity are provided. The proton exchange membrane composition includes a hyper-branched polymer, wherein the hyper-branched polymer has a DB (degree of branching) of more than 0.5. A polymer with high ion conductivity is distributed uniformly over the hyper-branched polymer, wherein the hyper-branched polymer has a weight ratio equal to or more than 5 wt %, based on the solid content of the proton exchange membrane composition.

Abstract translation: 提供了具有高质子传导性的质子交换膜组合物。 质子交换膜组合物包括超支化聚合物，其中超支化聚合物具有大于0.5的DB（支化度）。 具有高离子电导率的聚合物均匀地分布在超支化聚合物上，其中基于质子交换膜组合物的固体含量，超支化聚合物的重量比等于或大于5重量％。

公开(公告)号：US20100059737A1

公开(公告)日：2010-03-11

申请号：US12205585

申请日：2008-09-05

Applicant: Krishna Kumar Bhuwalka ,  Chin-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

Inventor： Krishna Kumar Bhuwalka ,  Chin-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

IPC: H01L29/15

CPC classification number: H01L29/7391 ,  H01L21/26586

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

Abstract translation: 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。

公开(公告)号：US20090277680A1

公开(公告)日：2009-11-12

申请号：US12346804

申请日：2008-12-30

Applicant: WEN-CHIN LEE ,  CHENG-HSIEN LIN

Inventor： WEN-CHIN LEE ,  CHENG-HSIEN LIN

IPC: H05K9/00 ,  B32B27/06

CPC classification number: H05K3/4641 ,  B82Y10/00 ,  H05K1/056 ,  H05K9/0088 ,  H05K2201/026 ,  H05K2201/0323 ,  Y10S977/70 ,  Y10S977/701 ,  Y10S977/712 ,  Y10S977/734 ,  Y10T428/24116 ,  Y10T428/30 ,  Y10T442/10

Abstract: An insulating film includes a first polymer layer, a second polymer layer and an electromagnetic shielding layer sandwiched between the first polymer layer and the second polymer layer. The electromagnetic shielding layer includes a number of carbon nanotube films that are substantially parallel to the first and second polymer layer. Each of the carbon nanotube films includes a number of carbon nanotubes that are substantially parallel to each other. The insulating film can provide anti-EMI effect in printed circuit boards without employing additional electromagnetic shielding layers.

Abstract translation: 绝缘膜包括第一聚合物层，第二聚合物层和夹在第一聚合物层和第二聚合物层之间的电磁屏蔽层。 电磁屏蔽层包括大致平行于第一和第二聚合物层的多个碳纳米管薄膜。 每个碳纳米管膜包括基本上彼此平行的多个碳纳米管。 绝缘膜可以在印刷电路板中提供抗电磁效应，而不需要额外的电磁屏蔽层。

公开(公告)号：US20090231490A1

公开(公告)日：2009-09-17

申请号：US12132078

申请日：2008-06-03

Applicant: Huang-Bin CHEN ,  Wen-Chin LEE ,  Tien-Hsin KUO

Inventor： Huang-Bin CHEN ,  Wen-Chin LEE ,  Tien-Hsin KUO

IPC: H04N7/00

CPC classification number: H04N5/44513 ,  H04N21/4345 ,  H04N21/435 ,  H04N21/4858 ,  H04N21/4884

Abstract: A method for automatically changing caption display style based on program content is disclosed. Plural caption parameters for each program content type are pre-defined. When a TV program is switched, a program system information protocol (PSIP) is searched to confirm program content type of the TV program. Captions of the TV program are decoded using a caption decoder based on program content type and corresponding caption parameters and the captions of the TV program are displayed according to the caption parameters relating to the program content type.

Abstract translation: 公开了一种基于节目内容自动改变字幕显示风格的方法。 每个节目内容类型的多个字幕参数是预先定义的。 当切换电视节目时，搜索节目系统信息协议（PSIP）以确认电视节目的节目内容类型。 使用基于节目内容类型和相应的标题参数的字幕解码器解码电视节目的标题，并且根据与节目内容类型相关的标题参数来显示电视节目的标题。

公开(公告)号：US20090140351A1

公开(公告)日：2009-06-04

申请号：US11948823

申请日：2007-11-30

Applicant: Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

Inventor： Hong-Nien Lin ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming a slim spacer on sidewalls of the gate dielectric and the gate electrode; forming a silicon carbon (SiC) region adjacent the slim spacer; forming a deep source/drain region comprising at least a portion of the silicon carbon region; blanket forming a metal layer, wherein a first interface between the metal layer and the deep source/drain is higher than a second interface between the gate dielectric and the semiconductor substrate; and annealing the semiconductor device to form a silicide region. Preferably, a horizontal spacing between an inner edge of the silicide region and a respective edge of the gate electrode is preferably less than about 150 Å.

Abstract translation: 一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅极电介质和所述栅电极的侧壁上形成细长间隔物; 形成邻近细长间隔物的硅碳（SiC）区域; 形成包含所述硅碳区域的至少一部分的深源极/漏极区域; 毯形成金属层，其中金属层和深源极/漏极之间的第一界面高于栅极电介质和半导体衬底之间的第二界面; 并对半导体器件进行退火以形成硅化物区域。 优选地，硅化物区域的内边缘和栅电极的相应边缘之间的水平间隔优选小于约150埃。

公开(公告)号：US07538398B2

公开(公告)日：2009-05-26

申请号：US11766773

申请日：2007-06-21

Applicant: Chung-Hu Ke ,  Ching-Ya Wang ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Ching-Ya Wang ,  Wen-Chin Lee

IPC: H01L29/417

CPC classification number: H01L23/485 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76844 ,  H01L21/7685 ,  H01L21/76885 ,  H01L29/456 ,  H01L29/6659 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a semiconductor source/drain contact structure, which comprises a substrate, a source/drain region disposed in the substrate, at least one non-silicided conductive layer including a barrier layer disposed over and in contact with the source/drain region, and one or more contact hole filling metals disposed over and in contact with the at least one non-silicided conductive layer, wherein a first contact area between the at least one non-silicided conductive layer and the source/drain region is substantially larger than a second contact area between the one or more contact hole filling metals and the at least one non-silicided conductive layer.

Abstract translation: 本发明公开了一种半导体源极/漏极接触结构，其包括衬底，设置在衬底中的源极/漏极区域，至少一个非硅化的导电层，其包括设置在源极/漏极区域之上并与源极/漏极区域接触的阻挡层 以及设置在所述至少一个非硅化物导电层上并与所述至少一个非硅化物导电层接触的一个或多个接触孔填充金属，其中所述至少一个非硅化物导电层和所述源极/漏极区之间的第一接触面积基本上大于 所述一个或多个接触孔填充金属和所述至少一个非硅化物导电层之间的第二接触区域。