-
公开(公告)号：US20230002889A1
公开(公告)日：2023-01-05
申请号：US17850141
申请日：2022-06-27
Applicant: ASM IP Holding B.V.
Inventor： Dieter Pierreux , Werner Knaepen , Arjen Klaver , Lucian Jdira , Marina Mariano , Theodorus G.M. Oosterlaken , Herbert Terhorst , Bert Jongbloed , Subir Parui
Abstract: A chemical vapor deposition furnace for depositing silicon nitride films, is discloses. The furnace comprising a process chamber elongated in a substantially vertical direction and a wafer boat for supporting a plurality of wafers in the process chamber. A process gas injector is provided inside the process chamber extending in a substantially vertical direction over substantially a wafer boat height and comprising a feed end connected to a source of a silicon precursor and a source of a nitrogen precursor and a plurality of vertically spaced gas injection holes to provide gas from the feed end to the process chamber. The furnace may comprise a purge gas injection system to provide a purge gas into the process chamber near a lower end of the process chamber.
-
公开(公告)号：US11230766B2
公开(公告)日：2022-01-25
申请号：US15940729
申请日：2018-03-29
Applicant: ASM IP Holding B.V.
Inventor： Dieter Pierreux , Cornelis Thaddeus Herbschleb , Werner Knaepen , Bert Jongbloed , Steven Van Aerde , Kelly Houben , Theodorus Oosterlaken , Chris de Ridder , Lucian Jdira
IPC: C23C16/458 , C23C16/56 , C23C16/455 , C23C16/48 , C23C16/50 , C23C16/44
Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.
-
公开(公告)号：US20210348267A1
公开(公告)日：2021-11-11
申请号：US17316847
申请日：2021-05-11
Applicant: ASM IP Holding B.V.
Inventor： Charles Dezelah , Qi Xie , Petri Raisanen , Dieter Pierreux , Bert Jongbloed , Werner Knaepen , Eric James Shero
IPC: C23C16/02 , C23C16/44 , C23C16/455
Abstract: A method may comprise disposing vanadium tetrachloride in a delivery vessel; delivering the vanadium tetrachloride to a reaction chamber in fluid communication with the delivery vessel; mitigating the delivery of decomposition products of the vanadium tetrachloride to the reaction chamber; and/or applying the vanadium tetrachloride to a substrate disposed in the reaction chamber to form a layer comprising vanadium on the substrate.
-
54.发明申请公开(公告)号：US20210335615A1
公开(公告)日：2021-10-28
申请号：US17235990
申请日：2021-04-21
Applicant: ASM IP Holding B.V.
Inventor： Dieter Pierreux , Bert Jongbloed , Qi Xie , Giuseppe Alessio Verni
IPC: H01L21/285 , C23C16/455 , C23C16/52
Abstract: Disclosed are methods and systems for depositing layers comprising vanadium, nitrogen, and element selected from the list consisting of molybdenum, tantalum, niobium, aluminum, and silicon. The layers are deposited onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.
-
公开(公告)号：US20210327704A1
公开(公告)日：2021-10-21
申请号：US17141360
申请日：2021-01-05
Applicant: ASM IP Holding B.V.
Inventor： Amir Kajbafvala , Joe Margetis , Xin Sun , David Kohen , Dieter Pierreux
Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.
-
Patent Agency Ranking
公开(公告)号：US20210151315A1
公开(公告)日：2021-05-20
申请号：US17093224
申请日：2020-11-09
Applicant: ASM IP Holding B.V.
Inventor： Dieter Pierreux , Anna Trovato , Kelly Houben , Steven van Aerde , Bert Jongbloed , Wilco A. Verweij
IPC: H01L21/02 , H01L23/522 , H01L23/532 , H01L21/768 , H01L21/311 , H01L21/285
Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.
-
公开(公告)号：US10460932B2
公开(公告)日：2019-10-29
申请号：US15476702
申请日：2017-03-31
Applicant: ASM IP Holding B.V.
Inventor： Steven R. A. Van Aerde , Kelly Houben , Maarten Stokhof , Bert Jongbloed , Dieter Pierreux
Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.
-
公开(公告)号：US20190301014A1
公开(公告)日：2019-10-03
申请号：US15940729
申请日：2018-03-29
Applicant: ASM IP Holding B.V.
Inventor： Dieter Pierreux , Cornelis Thaddeus Herbschleb , Werner Knaepen , Bert Jongbloed , Steven Van Aerde , Kelly Houben , Theodorus Oosterlaken , Chris de Ridder , Lucian Jdira
IPC: C23C16/458 , C23C16/56 , C23C16/50 , C23C16/48 , C23C16/455
Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.
-
59.发明申请公开(公告)号：US20180286679A1
公开(公告)日：2018-10-04
申请号：US15476752
申请日：2017-03-31
Applicant: ASM IP Holding B.V.
Inventor： Kelly Houben , Steven R.A. Van Aerde , Maarten Stokhof , Bert Jongbloed , Dieter Pierreux , Werner Knaepen
IPC: H01L21/033
CPC classification number: H01L21/0337
Abstract: The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.
-
公开(公告)号：US20180286672A1
公开(公告)日：2018-10-04
申请号：US15476702
申请日：2017-03-31
Applicant: ASM IP Holding B.V.
Inventor： Steven R.A. Van Aerde , Kelly Houben , Maarten Stokhof , Bert Jongbloed , Dieter Pierreux
IPC: H01L21/02 , H01L21/324 , H01L21/306
Abstract: Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.
-
-
-
-
-
-
-
-
-
Search Results
90
records
(took 0.032 seconds)
