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111 条记录 (耗时 0.053 秒)

    Method for producing reduced iron
    51.
    发明授权
    Method for producing reduced iron 失效
    还原铁生产方法

    公开(公告)号：US06602320B2

    公开(公告)日：2003-08-05

    申请号：US09828950

    申请日：2001-04-10

    申请人： Kojiro Fuji ,  Hidetoshi Tanaka ,  Shoichi Kikuchi ,  Takaya Kitajima ,  Osamu Tsuchiya

    发明人： Kojiro Fuji ,  Hidetoshi Tanaka ,  Shoichi Kikuchi ,  Takaya Kitajima ,  Osamu Tsuchiya

    IPC分类号： C21B1308

    CPC分类号： C21B13/10 ,  C21B13/105 ,  Y02P10/136

    摘要： A method for producing reduced iron comprises agglomerating a raw material mixture containing a carbonaceous reducing agent and an iron oxide-containing material into small agglomerates, heating the agglomerate within a heat reduction furnace, thereby solid reducing the iron oxide in the agglomerate to produce solid reduced iron, or further heating the solid reduced iron, melting the metallic iron produced by the reduction, and coagulating the molten metallic iron while separating the slag component contained in the small agglomerates to provide granular metallic iron, which is characterized by using a agglomerate having a particle size of 10 mm or less or 3-7 mm, preferably less than 6 mm, more preferably 3 mm or more and less than 6 mm as the small agglomerates.

    摘要翻译： 一种还原铁的制造方法包括将含有碳质还原剂和含铁氧化物的原料混合物凝集成小团聚物，在热还原炉内加热附聚物，由此固体还原附聚物中的氧化铁以产生固体还原 铁，或进一步加热固体还原铁，熔化通过还原产生的金属铁，并使熔融的金属铁凝结，同时分离包含在小团块中的炉渣成分，以提供粒状金属铁，其特征在于使用具有 粒径为10mm以下或3-7mm，优选小于6mm，更优选为3mm以上且小于6mm。

    Method of producing iron nuggets
    52.
    发明授权
    Method of producing iron nuggets 有权

    公开(公告)号：US06592649B2

    公开(公告)日：2003-07-15

    申请号：US09892546

    申请日：2001-06-28

    申请人： Shoichi Kikuchi ,  Yasuhiro Tanigaki ,  Koji Tokuda ,  Osamu Tsuchiya ,  Shuzo Ito

    发明人： Shoichi Kikuchi ,  Yasuhiro Tanigaki ,  Koji Tokuda ,  Osamu Tsuchiya ,  Shuzo Ito

    IPC分类号： C21B1100

    CPC分类号： C21B13/10 ,  C21B13/105 ,  Y02P10/136 ,  Y02P10/216

    摘要： The present invention provides a method of producing metallic iron nuggets with a high yield and good productivity, and more particularly a method which can produce metallic iron nuggets which have a high Fe purity and are excellent in transporting and handling due to a large grain diameter with a high yield and good productivity, when they are produced by reducing and melting raw material containing iron oxide such as iron ore and carbonaceous reducing agent such as coke. The method of producing metallic iron nuggets comprises steps of: heating raw material containing carbonaceous reducing agent and iron oxide-containing material in a reducing/melting furnace, reducing iron oxide in the raw material, and then heating and melting the metallic iron produced by the reduction and simultaneously making it coalesce while separating the metallic iron nuggets from slag components characterized in that the fixed carbon content ratio as the carbonaceous reducing agent is at least 73% and the volatile matter content in the raw material is not more than 3.9% are used, and the mixing content of carbonaceous reducing agent is restrained to be not more than 45% in relation to the iron oxide components, which is contained in the iron oxide-containing material of the raw material.

    Semiconductor device including arrangement for reducing junction degradation
    57.
    发明授权
    Semiconductor device including arrangement for reducing junction degradation 失效
    半导体器件包括用于减少结退化的装置

    公开(公告)号：US5426326A

    公开(公告)日：1995-06-20

    申请号：US103206

    申请日：1993-08-09

    申请人： Kiyonori Ohyu ,  Kozo Watanabe ,  Osamu Tsuchiya ,  Kazuyoshi Oshima ,  Yoshifumi Kawamoto ,  Atsushi Hiraiwa ,  Takashi Nishida

    发明人： Kiyonori Ohyu ,  Kozo Watanabe ,  Osamu Tsuchiya ,  Kazuyoshi Oshima ,  Yoshifumi Kawamoto ,  Atsushi Hiraiwa ,  Takashi Nishida

    IPC分类号： H01L27/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/78 ,  H01L29/165

    CPC分类号： H01L29/0847 ,  H01L29/08 ,  H01L29/36

    摘要： An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided:4.3.times.10.sup.12 (/cm.sup.2).gtoreq.An.multidot.Xn.sup.2 =Ap.multidot.Xp.sup.2Preferably, the p-n junction layer is formed under a contact hole of a source or drain region if the device in question is a MOSFET. As a result of using this arrangement, the leakage current caused by a local Zener effect decreases so that the electric field locally increased by the precipitate will not be greater than 1 MV/cm.

    摘要翻译： 提供了一种布置，以减少由半导体器件中的p-n结处的漏电流引起的结劣化。 这种布置对于各种器件可能是有用的，并且对于降低MOSFET的源极或漏极区域处的结退化特别有效。 为了实现这种减少，在半导体区域和衬底的p-n结处提供p-n结层。 pn结层的p型层和n型层的载流子浓度分布被设定为使得由于沉淀引起的在pn结的耗尽层中的局部电场增强倾向于增加的电场 从半导体表面引入的电流不超过1MV / cm。 当p型层或n型层的耗尽层的深度被称为Xp或Xn以及载流子浓度Ap或An的斜率时，提供以下关系：4.3×10 12（/ cm 2） ）> / = AnxXn2 = ApxXp2如果所讨论的器件是MOSFET，则优选地，在源极或漏极区域的接触孔下方形成pn结层。 作为使用这种布置的结果，由局部齐纳效应引起的漏电流减小，使得由沉淀物局部增加的电场将不会大于1MV / cm。

    Process for producing semiconductor memory device
    58.
    发明授权
    Process for producing semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US5079181A

    公开(公告)日：1992-01-07

    申请号：US397847

    申请日：1989-08-24

    申请人： Shinji Shimizu ,  Osamu Tsuchiya ,  Katsuyuki Sato

    发明人： Shinji Shimizu ,  Osamu Tsuchiya ,  Katsuyuki Sato

    IPC分类号： G11C7/18 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  G11C7/18 ,  H01L27/10805 ,  H01L29/66181 ,  Y10S257/906

    摘要： Dynamic RAM having memory cells, each of the memory cells having a capacitor with the electrode comprised of a first semiconductor region of a first type of conductivity formed in a substrate of second conductivity type. The first semiconductor region is formed by introducing impurities using a mask comprising (1) a nitride film which is deposited so as to define part of the shape of the capacitor. An oxide film, formed by thermal oxidation of the substrate, defines the shape of the memory cells, and each of the memory cells further have at least a second semiconductor region of a second type of conductivity formed between and under the electrodes, the shape thereof being defined by the nitride film and the oxide film that is formed by thermal oxidation.

    Method of making semiconductor integrated circuit device with polysilicon contacts
    59.
    发明授权
    Method of making semiconductor integrated circuit device with polysilicon contacts 失效
    制造具有多晶硅接触的半导体集成电路器件的方法

    公开(公告)号：US5025741A

    公开(公告)日：1991-06-25

    申请号：US344404

    申请日：1989-04-28

    申请人： Naokatsu Suwanai ,  Osamu Tsuchiya

    发明人： Naokatsu Suwanai ,  Osamu Tsuchiya

    IPC分类号： H01L23/52 ,  H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/532 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/43

    CPC分类号： H01L21/28525 ,  H01L21/2022 ,  H01L21/32055 ,  H01L23/53271 ,  H01L2924/0002

    摘要： A semiconductor integrated circuit device having a wiring line of aluminum film or aluminum alloy film covered with a silicon insulation film and connected to the semiconductor region formed on the principal surface of a single crystal silicon substrate, with a polycrystalline silicon film interposed, wherein said silicon film is a polycrystalline silicon film composed of large crystal grains which is formed by depositing in amorphous state and then heat-treating the deposited film, said polycrystalline silicon film reduces the amount of silicon atoms which separates out in said wiring line. Also said wiring line is provided with a shielding film which is disposed between said insulation film and at least the upper surface and lower surface of said wiring line and which prevents silicon atoms from separating out from said insulation film.A process for manufacturing a semiconductor integrated circuit device which comprises the steps of depositing an amorphous silicon film on the principal surface of said semiconductor region, and performing heat treatment on said silicon film, thereby converting the amorphous silicon film into a polycrystalline silicon film composed of large crystal grains.

    摘要翻译： 一种半导体集成电路器件，其具有覆盖有硅绝缘膜的铝膜或铝合金膜的布线，并且与形成在单晶硅衬底的主表面上的半导体区域连接，并插入多晶硅膜，其中所述硅 膜是由非晶态沉积形成的大晶粒构成的多晶硅膜，然后对沉积膜进行热处理，所述多晶硅膜减少了在所述布线中分离的硅原子的量。 所述布线还设置有屏蔽膜，所述屏蔽膜设置在所述绝缘膜和所述布线的至少所述上表面和下表面之间，并且防止硅原子与所述绝缘膜分离。 一种制造半导体集成电路器件的方法，包括以下步骤：在所述半导体区域的主表面上沉积非晶硅膜，并对所述硅膜进行热处理，从而将非晶硅膜转化为由 大晶粒。

    Semiconductor integrated circuit device
    60.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US4967396A

    公开(公告)日：1990-10-30

    申请号：US471073

    申请日：1990-01-29

    申请人： Kazuhiko Kajigaya ,  Osamu Tsuchiya

    发明人： Kazuhiko Kajigaya ,  Osamu Tsuchiya

    IPC分类号： G11C11/401 ,  G11C11/408 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G11C11/408 ,  H01L23/5222 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/911

    摘要： The present invention relates to a dynamic type RAM and, more particularly, to a dynamic type RAM formed using one-element type dynamic memory cells each comprised of a data storing capacitor and an address selecting MOSFET. Divided word lines are arranged such that one divided word line intersects another at a point of discontinuity of the other divided word line adjacent to a joint of the one divided word line to the corresponding word line. This prevents generation of an array noise due to coupling capacitances, and thus improves the read margin.

    摘要翻译： 本发明涉及一种动态型RAM，更具体地说，涉及一种使用由数据存储电容器和地址选择MOSFET构成的单元型动态存储单元形成的动态型RAM。 分割字线被布置成使得一条分割字线在与分开的一条划分字线的关节相邻的另一分割字线的不连续点与相应字线相交。 这防止由于耦合电容而产生阵列噪声，并且因此改善了读取余量。