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    Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method
    51.
    发明授权
    Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method 失效
    使用金属吸气塞形成高导电性金属互连的方法和执行该方法的系统

    公开(公告)号：US5994206A

    公开(公告)日：1999-11-30

    申请号：US944170

    申请日：1997-10-06

    申请人： Subhash Gupta ,  Susan Hsuching Chen

    发明人： Subhash Gupta ,  Susan Hsuching Chen

    IPC分类号： H01L21/768 ,  H01L21/225 ,  H01L21/385

    CPC分类号： H01L21/76877 ,  H01L21/76802

    摘要： A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole on tope of the high conductivity metal. The via structure further includes a via plug material covering the high conductivity metal and substantially filling the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the via hole. Accordingly, by providing a via plug material within the via hole, the via plug material getters or dissolves the high conductivity metal that reaches the sidewalls of the dielectric layer during the via etch and sputter etch processes and the junction poisoning problems associated therewith are substantially minimized.

    摘要翻译： 公开了一种用于为集成电路的高导电性金属提供通孔结构的方法和系统。 在第一方面，该方法和系统包括将光致抗蚀剂材料和电介质材料蚀刻到高导电性金属上以形成通孔。 通孔包括在侧壁上的溅射的高导电性金属。 该方法和系统还包括在通孔内提供通孔塞材料。 小瓶插头材料基本上覆盖高导电性金属的基部和通孔的侧壁。 通孔插塞材料还能够吸收或溶解溅射在电介质材料的侧壁上的高导电性金属。 在第二方面中，根据本发明公开了一种用于集成电路的通孔结构。 通孔结构包括高导电性金属和围绕高导电性金属的介电材料。 电介质材料包括在高导电性金属的顶部上形成通孔的侧壁。 通孔结构还包括覆盖高导电性金属并基本上填充通孔的通孔塞材料。 通孔插塞材料还能够吸收或溶解溅射在通孔的侧壁上的高导电性金属。 因此，通过在通孔内提供通孔插塞材料，通孔插塞材料在通孔蚀刻和溅射蚀刻工艺期间吸收或溶解到达介电层侧壁的高导电性金属，并且与之相关的结中毒问题基本上最小化 。

    Deep UV anti-reflection coating etch
    52.
    发明授权
    Deep UV anti-reflection coating etch 失效
    深UV抗反射涂层蚀刻

    公开(公告)号：US5910453A

    公开(公告)日：1999-06-08

    申请号：US584941

    申请日：1996-01-16

    申请人： Subhash Gupta ,  Mutya Vicente

    发明人： Subhash Gupta ,  Mutya Vicente

    IPC分类号： H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L21/312 ,  H01L21/302

    CPC分类号： H01L21/0276 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/31116 ,  H01L21/312

    摘要： An etching process for DUV photolithography is provided for etching a layer of anti-reflection coating (ARC) comprising spin-on organic ARC material which is formed beneath a layer of photoresist. After patterning the layer of photoresist, the layer of ARC is etched by employing a mixture of oxygen plasma, nitrogen plasma, and at least one inert gas. Anisotropic etching of the layer of ARC is provided with the process of the present invention. In comparison with prior art etching processes for etching a layer of ARC, the process of the present invention provides a favorable etch rate with improved selectivity over the etching of the layer of photoresist. The layer of ARC is etched without causing lateral erosion of the layer of photoresist. Faceting of the top edges of the corners of the layer of photoresist is also minimized. The profile of the layer of photoresist is essentially maintained thereby enabling for critical dimension fidelity. The process of the present invention is residue-free, and provides favorable selectivity for etching the layer of ARC over most underlying materials conventionally used in integrated circuit structures. The layer of ARC can also be etched by employing a mixture of nitrogen plasma and inert gas. Employing a mixture of nitrogen plasma and inert gas, without oxygen plasma, provides a reduced etch rate.

    摘要翻译： 提供了用于DUV光刻的蚀刻工艺，用于蚀刻包含形成在光致抗蚀剂层下面的旋涂有机ARC材料的抗反射涂层（ARC）层。 在图案化光致抗蚀剂层之后，通过使用氧等离子体，氮等离子体和至少一种惰性气体的混合物蚀刻ARC层。 本发明的方法提供了ARC层的各向异性蚀刻。 与用于蚀刻ARC层的现有技术的蚀刻工艺相比，本发明的方法提供了对蚀刻光致抗蚀剂层的优选蚀刻速率。 蚀刻ARC层，不会引起光致抗蚀剂层的横向侵蚀。 光致抗蚀剂层的角部的顶部边缘的表面也被最小化。 基本上保持光致抗蚀剂层的轮廓，从而能够实现临界尺寸保真度。 本发明的方法是无残留的，并且为通常用于集成电路结构的大多数底层材料提供了对ARC层蚀刻的良好选择性。 也可以通过使用氮等离子体和惰性气体的混合物来蚀刻ARC层。 使用无等离子体的氮等离子体和惰性气体的混合物提供降低的蚀刻速率。

    Dual damascene with a protective mask for via etching
    54.
    发明授权
    Dual damascene with a protective mask for via etching 失效
    双镶嵌带防蚀口罩，用于通孔蚀刻

    公开(公告)号：US5686354A

    公开(公告)日：1997-11-11

    申请号：US478324

    申请日：1995-06-07

    申请人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

    发明人： Steven Avanzino ,  Subhash Gupta ,  Rich Klein ,  Scott D. Luning ,  Ming-Ren Lin

    IPC分类号： H01L21/768 ,  H01L21/28

    CPC分类号： H01L21/76831 ,  H01L21/76807

    摘要： A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.

    摘要翻译： 一种双镶嵌方法，用于制造导线的互连级别并且连接用于集成电路的绝缘和用于半导体器件的衬底载体的通孔，其使用薄的保护性通孔掩模形成通孔。 导电线掩模图案用于在绝缘层中形成导电线路开口。 接下来，在导电线路开口中沉积有保形材料的薄保护层。 保护层和绝缘层各自具有对其它蚀刻剂的耐蚀刻性。 使用通孔掩模图案，开口蚀刻保护层，绝缘层用作蚀刻停止。 接下来通过开口被蚀刻在绝缘材料中，使用薄保护层中的开口作为蚀刻掩模。 如果保护层是导电材料，则在导电线之前或之后将其从绝缘层的表面去除，并且通孔开口填充有导电材料。 如果保护材料是绝缘材料，则在填充导电线和通孔开口导电材料之前将其完全去除。

    Methods for using a processor array to perform matrix calculations
    55.
    发明授权
    Methods for using a processor array to perform matrix calculations 失效
    使用处理器阵列执行矩阵计算的方法

    公开(公告)号：US5319586A

    公开(公告)日：1994-06-07

    申请号：US18343

    申请日：1993-02-16

    申请人： Subhash Gupta ,  Ravi Mehrotra

    发明人： Subhash Gupta ,  Ravi Mehrotra

    IPC分类号： G06F17/12 ,  G06F17/16 ,  G06F15/32 ,  G06F7/00

    CPC分类号： G06F17/12 ,  G06F17/16

    摘要： An apparatus and method for performing matrix calculations is provided. The apparatus comprises a computer system having a linearly connected array of processors. Each processor has three inputs, two of which receive data along the linear array. The processors are configured to perform certain multiply-add operations. The methods permit speeded up solution of systems of linear equations and matrix inversion. The methods involve manipulating the matrices and the unknown vector values such that the problem can be solved using vector orthogonalization techniques.

    摘要翻译： 提供了一种用于执行矩阵计算的装置和方法。 该装置包括具有线性连接的处理器阵列的计算机系统。 每个处理器有三个输入，其中两个输入沿线性阵列接收数据。 处理器被配置为执行某些乘法加法操作。 该方法允许加速线性方程组和矩阵反演系统的解。 该方法涉及操纵矩阵和未知向量值，使得可以使用向量正交化技术来解决问题。

    Etch stop layer using polymers
    56.
    发明授权
    Etch stop layer using polymers 失效
    使用聚合物的蚀刻停止层

    公开(公告)号：US5198298A

    公开(公告)日：1993-03-30

    申请号：US426147

    申请日：1989-10-24

    申请人： Jacob D. Haskell ,  Subhash Gupta

    发明人： Jacob D. Haskell ,  Subhash Gupta

    IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/76801 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76834 ,  Y10S438/97 ,  Y10T428/265 ,  Y10T428/31612 ,  Y10T428/31663

    摘要： An etch stop player (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').

    摘要翻译： 提供了用于允许在蚀刻期间区分两个相似层（20,24）（例如两个氧化物层）的蚀刻停止播放器（22）。 蚀刻停止层包括硅 - 卤氧化物聚合物，优选硅 - 氟氧化物聚合物。 使用聚合物作为蚀刻停止层允许金属导体表面（12,12'）和触点（14'）的更靠近的放置。

    Dopant-independent polysilicon plasma etch
    57.
    发明授权
    Dopant-independent polysilicon plasma etch 失效
    掺杂剂多晶硅等离子体蚀刻

    公开(公告)号：US4992134A

    公开(公告)日：1991-02-12

    申请号：US436282

    申请日：1989-11-14

    申请人： Subhash Gupta ,  Kashmir Sahota

    发明人： Subhash Gupta ,  Kashmir Sahota

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/3065 ,  H01L21/32137

    摘要： A plasma etching process is provided which etches n-type, p-type, and intrinsic polysilicon on the same wafer at substantially the same rate. Native oxide is first removed by etching in a conventional oxide etchant, such as SiCl.sub.4 /Cl.sub.2, BCl.sub.3 /Cl.sub.2, CCl.sub.4, other mixtures of fluorinated or chlorinated gases, and mixtures of Freon-based gases. The polysilicon is then etched in an etchant comprising at least about 75% hydrogen and the balance a halogen-containing fluid, such as chloride. The silicon etchant etches at a rate of about 300 to 500 .ANG. for a batch of 10 wafers, depending on hydrogen concentration, power, flow rate of gas mixture, and gas pressure.