公开(公告)号：US12249511B2

公开(公告)日：2025-03-11

申请号：US17192213

申请日：2021-03-04

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Lin Dong ,  Benjamin Colombeau ,  Johanes F. Swenberg ,  Linlin Wang

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/51

Abstract: A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-κ dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-κ dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-κ dielectric layer.

公开(公告)号：US20240332388A1

公开(公告)日：2024-10-03

申请号：US18609650

申请日：2024-03-19

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Benjamin Colombeau ,  Nicolas Breil ,  Ashish Pal ,  El Mehdi Bazizi ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthiharan ,  Pratik B. Vyas ,  Gregory Costrini

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.

公开(公告)号：US20240290884A1

公开(公告)日：2024-08-29

申请号：US18441824

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： El Mehdi Bazizi ,  Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Hui Zhao ,  Ashish Pal

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a stressed dielectric material having a stress of about 500 MPa or greater.

公开(公告)号：US20240234531A1

公开(公告)日：2024-07-11

申请号：US18538273

申请日：2023-12-13

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Liu Jiang ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  Benjamin Colombeau ,  El Mehdi Bazizi ,  Balasubramanian Pranatharthiharan

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

公开(公告)号：US20230178628A1

公开(公告)日：2023-06-08

申请号：US17967099

申请日：2022-10-17

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Lequn Liu

IPC: H01L29/66 ,  H01L21/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/66439 ,  H01L22/12 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.

公开(公告)号：US20230039074A1

公开(公告)日：2023-02-09

申请号：US17968068

申请日：2022-10-18

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US11495500B2

公开(公告)日：2022-11-08

申请号：US17073505

申请日：2020-10-19

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Hans-Joachim Gossmann

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L21/324 ,  H01L21/02

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US11443948B2

公开(公告)日：2022-09-13

申请号：US16536600

申请日：2019-08-09

Applicant: Applied Materials, Inc.

Inventor： Wolfgang Aderhold ,  Yi-Chiau Huang ,  Wei Liu ,  Benjamin Colombeau ,  Abhilash Mayur

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L21/02 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

公开(公告)号：US20220246742A1

公开(公告)日：2022-08-04

申请号：US17583355

申请日：2022-01-25

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau ,  Myungsun Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/15

Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices comprise a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

公开(公告)号：US11373871B2

公开(公告)日：2022-06-28

申请号：US16577353

申请日：2019-09-20

Applicant: APPLIED MATERIALS, INC.

Inventor： Benjamin Colombeau ,  Wolfgang R. Aderhold ,  Andy Lo ,  Yi-Chiau Huang

IPC: H01L21/225 ,  H01L29/66 ,  H01L21/324 ,  H01L21/02

Abstract: Methods and apparatus for forming doped material layers in semiconductor devices using an integrated selective monolayer doping (SMLD) process. A concentration of dopant is deposited on a material layer using the SMLD process and the concentration of dopant is then annealed to diffuse the concentration of dopant into the material layer. The SMLD process conforms the concentration of dopant to a surface of the material layer and may be performed in a single CVD chamber. The SMLD process may also be repeated to further alter the diffusion parameters of the dopant into the material layer. The SMLD process is compatible with p-type dopant species and n-type dopant species.