公开(公告)号：US08013317B2

公开(公告)日：2011-09-06

申请号：US12408510

申请日：2009-03-20

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L29/02

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/105 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings. The plurality of layer selection transistors are connected to at least one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, and collectively selects the at least one in the same plane.

摘要翻译： 提供具有多个单位存储层的非易失性存储装置和多个层选择晶体管。 多个单元存储层在垂直于单元存储层的层表面的方向上层叠。 每个单元存储层包括多个第一布线，多个第二布线，其设置成不平行于多个第一布线，以及记录层，设置在多个第一布线和多个第二布线之间。 多个层选择晶体管连接到每个单元存储层的多个第一布线和多个第二布线中的至少一个，并且在同一平面中共同选择至少一个。

公开(公告)号：US07884413B2

公开(公告)日：2011-02-08

申请号：US12219880

申请日：2008-07-30

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi

IPC分类号： H01L29/788

CPC分类号： H01L21/022 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/312 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76837

摘要： A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film.

摘要翻译： 一种制造半导体器件的方法，包括在下面的区域上形成含有氧化硅作为主要成分的第一绝缘膜，将水粘附到第一绝缘膜上，在水溶性聚合物层上形成含有含硅聚合物的聚合物溶液层， 粘合的第一绝缘膜，并且从聚合物溶液层形成含有氧化硅作为主要成分的第二绝缘膜，其中形成所述第二绝缘膜包括通过所述聚合物和附着到所述第一绝缘膜的水之间的反应形成氧化硅。

公开(公告)号：US20110027981A1

公开(公告)日：2011-02-03

申请号：US12905255

申请日：2010-10-15

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion.

摘要翻译： 非易失性半导体存储装置包括：多个叠置的单元并置在基板的主表面上，每个堆叠单元在平行于基板的主表面的第一方向上对准; 以及在与第一方向不平行的第二方向上平行于主表面对准的栅电极。 多个堆叠单元中的每一个经由绝缘层包括多个层叠的半导体层。 多个堆叠单元并置，使得相邻层叠单元之间的间隔交替地为第一间隔，而第二间隔大于第一间隔。 第二间隔以比特线的半间距F的大小的四倍的周期性间隔提供。 栅电极包括进入堆叠单元之间的第二间隔的间隙的突出部分。 第一绝缘膜，电荷存储层和第二绝缘膜设置在半导体层的侧面和突出部之间。

公开(公告)号：US07855116B2

公开(公告)日：2010-12-21

申请号：US12209116

申请日：2008-09-11

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L21/8234

CPC分类号： H01L21/76229 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11573

摘要： In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.

摘要翻译： 在具有非易失性存储单元部分的非易失性半导体存储器件中，外围电路区域的低电压工作电路部分和形成在衬底上的外围电路区域的高电压工作电路部分，并且上述元件 部分通过填充绝缘膜彼此隔离，高压操作电路部分中的填充绝缘膜的上表面位于基板的表面上方，并且至少部分填充绝缘膜的上表面在低 电压操作电路部分被拉回到比基板的表面低的部分。

公开(公告)号：US07851849B2

公开(公告)日：2010-12-14

申请号：US12476799

申请日：2009-06-02

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L23/62

CPC分类号： H01L27/11582 ,  H01L27/11573 ,  H01L27/11578

摘要： A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion.

摘要翻译： 非易失性半导体存储装置包括：多个叠置的单元并置在基板的主表面上，每个堆叠单元在平行于基板的主表面的第一方向上对准; 以及在与第一方向不平行的第二方向上平行于主表面对准的栅电极。 多个堆叠单元中的每一个经由绝缘层包括多个层叠的半导体层。 多个堆叠单元并置，使得相邻层叠单元之间的间隔交替地为第一间隔，而第二间隔大于第一间隔。 第二间隔以比特线的半间距F的大小的四倍的周期性间隔提供。 栅电极包括进入堆叠单元之间的第二间隔的间隙的突出部分。 第一绝缘膜，电荷存储层和第二绝缘膜设置在半导体层的侧面和突出部之间。

公开(公告)号：US07618876B2

公开(公告)日：2009-11-17

申请号：US11227252

申请日：2005-09-16

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

IPC分类号： H01L21/76 ,  H01L21/44

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成沟槽，在沟槽中形成具有第一凹陷部分的第一绝缘膜，形成涂膜以便将其涂覆在第一凹部中，将涂膜转变为 第二绝缘膜，平坦化第二绝缘膜以暴露第一绝缘膜和第二绝缘膜，至少从第一凹部去除第二绝缘膜，以调节形成在沟槽中的第一凹部的纵横比，由此形成 在其中形成第二凹部，在半导体衬底的表面上形成第三绝缘膜，以便填充第二凹部。

公开(公告)号：US20070224749A1

公开(公告)日：2007-09-27

申请号：US11798956

申请日：2007-05-18

申请人： Takeshi Hoshi ,  Masahiro Kiyotoshi

发明人： Takeshi Hoshi ,  Masahiro Kiyotoshi

IPC分类号： H01L21/336

CPC分类号： C23C18/125 ,  C23C18/06 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1275 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/3141 ,  H01L21/31612

摘要： According to the present invention, there is provided a semiconductor device fabrication method having: coating a semiconductor substrate with a silazane perhydride polymer solution prepared by dispersing a silazane perhydride polymer in a solvent containing carbon, thereby forming a coating film; forming a polysilazane film by volatilizing the solvent by heat-treating the coating film; and inserting the semiconductor substrate into a predetermined furnace, lowering a pressure in the furnace, and oxidizing the polysilazane film while the pressure in the furnace is raised by supplying steam into the furnace, thereby forming a silicon oxide film.

摘要翻译： 根据本发明，提供了一种半导体器件制造方法，其具有：通过将硅氮烷二酸酐聚合物分散在含有碳的溶剂中而制备的硅氮烷聚合物溶液涂覆半导体衬底，从而形成涂膜; 通过对涂膜进行热处理使溶剂挥发而形成聚硅氮烷膜; 并且将半导体衬底插入预定的炉中，降低炉中的压力，并且通过向炉中供应蒸汽来升高炉中的压力来氧化聚硅氮烷膜，由此形成氧化硅膜。

公开(公告)号：US07238587B2

公开(公告)日：2007-07-03

申请号：US11167233

申请日：2005-06-28

申请人： Takeshi Hoshi ,  Masahiro Kiyotoshi

发明人： Takeshi Hoshi ,  Masahiro Kiyotoshi

IPC分类号： H01L21/76

CPC分类号： C23C18/125 ,  C23C18/06 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1275 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/3141 ,  H01L21/31612

摘要： According to the present invention, there is provided a semiconductor device fabrication method that coats a semiconductor substrate with a silazane perhydride polymer solution prepared by dispersing a silazane perhydride polymer in a solvent containing carbon, thereby forming a coating film. A polysilazane film is formed by volatilizing the solvent by heat-treating the coating film. The semiconductor substrate is inserted into a predetermined furnace, where the pressure in the furnace is lowered. The polysilazane film is oxidized while the pressure in the furnace is raised by supplying steam into the furnace, thereby forming a silicon oxide film.

摘要翻译： 根据本发明，提供一种半导体器件的制造方法，该半导体器件制造方法通过将硅氮烷聚合物分散在含有碳的溶剂中而制备的硅氮烷聚合物溶液涂覆半导体衬底，从而形成涂膜。 通过对涂膜进行热处理使溶剂挥发而形成聚硅氮烷膜。 将半导体衬底插入预定的炉中，其中炉中的压力降低。 聚硅氮烷膜被氧化，同时通过向炉内供应蒸汽来升高炉中的压力，从而形成氧化硅膜。

公开(公告)号：US07187026B2

公开(公告)日：2007-03-06

申请号：US10721082

申请日：2003-11-26

申请人： Masahiro Kiyotoshi

发明人： Masahiro Kiyotoshi

IPC分类号： H01L27/108

CPC分类号： H01L28/82 ,  H01L21/8221 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/0805 ,  H01L28/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor structure formed above the semiconductor substrate and comprising a first electrode, a second electrode provided below the first electrode, a third electrode provided below the second electrode, a first dielectric film provided between the first electrode and the second electrode, and a second dielectric film provided between the second electrode and the third electrode, an insulating film covering the capacitor structure and having a first hole reaching the first electrode, a second hole reaching the second electrode, and a third hole reaching the third electrode, a first conductive connection electrically connecting the first electrode and the third electrode and having portions buried in the first and third holes, and a second conductive connection formed-separately from the first conductive connection and having a portion buried in the second hole.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，形成在半导体衬底上方的电容器结构，包括第一电极，设置在第一电极下方的第二电极，设置在第二电极下方的第三电极，设置在第一电极之间的第一电介质膜 电极和第二电极，以及设置在第二电极和第三电极之间的第二电介质膜，覆盖电容器结构的绝缘膜，具有到达第一电极的第一孔，到达第二电极的第二孔和第三孔 到达第三电极，电连接第一电极和第三电极并且具有埋在第一和第三孔中的部分的第一导电连接，以及与第一导电连接分开形成并具有埋在第二电极中的部分的第二导电连接 孔。

公开(公告)号：US20060270170A1

公开(公告)日：2006-11-30

申请号：US11227252

申请日：2005-09-16

申请人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

发明人： Osamu Arisumi ,  Masahiro Kiyotoshi ,  Katsuhiko Hieda ,  Yoshitaka Tsunashima

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底中形成沟槽，在沟槽中形成具有第一凹陷部分的第一绝缘膜，形成涂膜以便将其涂覆在第一凹部中，将涂膜转变为 第二绝缘膜，平坦化第二绝缘膜以暴露第一绝缘膜和第二绝缘膜，至少从第一凹部去除第二绝缘膜，以调节形成在沟槽中的第一凹部的纵横比，由此形成 在其中形成第二凹部，在半导体衬底的表面上形成第三绝缘膜，以便填充第二凹部。