公开(公告)号：US07936612B2

公开(公告)日：2011-05-03

申请号：US12654338

申请日：2009-12-17

申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

摘要翻译： 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

公开(公告)号：US07889548B2

公开(公告)日：2011-02-15

申请号：US12585637

申请日：2009-09-21

申请人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Ji-Hye Yi ,  Beak-Hyung Cho

发明人： Chang-Wook Jeong ,  Jun-Hyok Kong ,  Ji-Hye Yi ,  Beak-Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C2013/0083 ,  Y10S977/754

摘要： According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.

摘要翻译： 根据一个实施方案，包括第一结晶相的至少一部分相变材料转化为第二结晶相和非晶相之一。 第二结晶相比第一结晶相更容易转变成非晶态。 例如，第一结晶相可以是六方密封填充结构，并且第一结晶相可以是面心立方结构。

公开(公告)号：US20100097850A1

公开(公告)日：2010-04-22

申请号：US12611606

申请日：2009-11-03

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

摘要翻译： 提供了使用相变存储器件的装置和系统。 相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多个复位线中相应的一个。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

公开(公告)号：US20090316474A1

公开(公告)日：2009-12-24

申请号：US12457319

申请日：2009-06-08

申请人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

发明人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

IPC分类号： G11C11/00 ,  G11C29/00

CPC分类号： G11C29/808 ,  G11C13/0004

摘要： The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

摘要翻译： 所述相变存储器件包括多个存储体，连接到所述多个存储体的多个局部导体线，连接到所述多个局部导体线的至少一个全局导体线，以及至少一个修理控制电路， 选择性地将所述至少一个全局导体线中的至少一个与至少一个冗余全局导体线替换并且被配置为用至少一个冗余局部导体线选择性地替换所述多条局部导体线中的至少一个。

公开(公告)号：US20080106922A1

公开(公告)日：2008-05-08

申请号：US11735635

申请日：2007-04-16

申请人： Joon-Min Park ,  Byung-Gil Choi ,  Du-Eung Kim ,  Beak-Hyung Cho

发明人： Joon-Min Park ,  Byung-Gil Choi ,  Du-Eung Kim ,  Beak-Hyung Cho

IPC分类号： G11C5/06 ,  G11C11/00

CPC分类号： G11C11/16 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/76

摘要： A semiconductor memory device and a layout structure of word line contacts, in which the semiconductor memory device includes an active region, a plurality of memory cells, and word line contacts. The active region is disposed in a first direction as a length direction on a semiconductor substrate and is used as a word line. The plurality of memory cells are disposed in the first direction on the active region and are each constructed of one variable resistance device and one diode device. In the word line contacts, at least one each is disposed between respective units, wherein each unit is constructed of predetermined numbers of memory cells on the active region. A bridge effect, such as a short-circuit between adjacent word lines, can be prevented or substantially reduced.

摘要翻译： 半导体存储器件和字线触点的布局结构，其中半导体存储器件包括有源区，多个存储单元和字线触点。 有源区域沿着半导体衬底上的长度方向的第一方向设置，并用作字线。 多个存储单元在有源区域上沿第一方向设置，并且分别由一个可变电阻器件和一个二极管器件构成。 在字线触点中，每个单元之间至少设置一个，其中每个单元由有源区上的预定数量的存储单元构成。 可以防止或显着减少诸如相邻字线之间的短路的桥接效应。

公开(公告)号：US07304885B2

公开(公告)日：2007-12-04

申请号：US11074557

申请日：2005-03-08

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Phase-change memory devices are provided that include a plurality of phase-change memory cells and a reset pulse generation circuit configured to output a plurality of sequential reset pulses. Each sequential reset pulse is output to a corresponding one of a plurality of reset lines. A plurality of write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. Methods of programming phase-change memory devices using sequential reset control signals are also provided.

摘要翻译： 提供了包括多个相变存储器单元的相变存储器件和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多条复位线中相应的一条。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。 还提供了使用顺序复位控制信号编程相变存储器件的方法。

公开(公告)号：US20070189104A1

公开(公告)日：2007-08-16

申请号：US11787931

申请日：2007-04-18

申请人： Beak-Hyung Cho ,  Du-Eung Kim

发明人： Beak-Hyung Cho ,  Du-Eung Kim

IPC分类号： G11C8/00

CPC分类号： G11C13/0028 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004

摘要： A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.

摘要翻译： 存储器件包括多个块，每个块具有相应的存储器单元阵列和相应的本地字线。 存储器件还包括耦合在每个本地字线和公共电压节点之间的相应开关器件。 全局字线驱动器控制相应的开关装置对跨越包括访问的存储器单元的块的行中的相应本地字线导通。 因此，公共电压节点处于被访问的存储器单元的当前路径中，具有最小的布局面积和当前路径的电阻。

公开(公告)号：US07215592B2

公开(公告)日：2007-05-08

申请号：US11035205

申请日：2005-01-12

申请人： Beak-Hyung Cho ,  Du-Eung Kim

发明人： Beak-Hyung Cho ,  Du-Eung Kim

IPC分类号： G11C8/00 ,  G11C7/00

CPC分类号： G11C13/0028 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004

摘要： A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.

公开(公告)号：US20060186483A1

公开(公告)日：2006-08-24

申请号：US11324112

申请日：2005-12-30

申请人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

发明人： Woo-Yeong Cho ,  Du-Eung Kim ,  Yun-Seung Shin ,  Hyun-Geun Byun ,  Sang-Beom Kang ,  Beak-Hyung Cho ,  Choong-Keun Kwak

IPC分类号： H01L29/76

CPC分类号： G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.

摘要翻译： 提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型 从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型 具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和 第二半导体之间的间隙区域 多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

公开(公告)号：US20050195633A1

公开(公告)日：2005-09-08

申请号：US11070196

申请日：2005-03-03

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak ,  Beak-Hyung Cho

IPC分类号： G11C13/02 ,  G11C13/00 ,  G11C16/02 ,  G11C16/10 ,  G11C19/08 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2013/0092

摘要： A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

摘要翻译： 一种用于编程相变存储器阵列和相变存储器件的电路的方法，每个相变存储器件具有多个相变存储器单元，可以使其中的所有相变存储器单元能够被改变或设置为设定电阻 状态，并且可以减少将相变存储器阵列改变为设定电阻状态所需的时间。 在该方法中，可以将具有第一至第n个阶段的设定电流脉冲施加到阵列的单元以将单元改变为设定电阻状态。 施加到任何阶段中的相变存储器单元的设定电流脉冲的最小电流电平可以高于阵列的单元的参考电流电平。 设定电流脉冲的给定电流电平可以从一个阶段顺序地减少。