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公开(公告)号：US10375493B2
公开(公告)日：2019-08-06
申请号：US16009638
申请日：2018-06-15
Inventor： John Paul Lesso , Yanto Suryono
IPC: H04R29/00 , H04R3/04 , G10L19/12 , G01R31/3167 , G10L19/04
Abstract: An audio system receives an input signal and, if the input signal has a sparse representation in the frequency domain, comprising components at at least one frequency of interest, the input signal is filtered in at least one band pass filter, such that only components at the or each frequency of interest are passed to an output. The operation is able in some case to analyze the input signal to determine whether the input signal has a sparse representation in the frequency domain.
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公开(公告)号：US10263633B2
公开(公告)日：2019-04-16
申请号：US15991619
申请日：2018-05-29
Inventor： John Paul Lesso , David Paul Singleton
Abstract: This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse-width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN).
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公开(公告)号：US10003344B2
公开(公告)日：2018-06-19
申请号：US15009405
申请日：2016-01-28
Inventor： John Paul Lesso
CPC classification number: H03L7/099 , G06F3/162 , H03G5/00 , H03G5/005 , H03L7/08 , H03L7/087 , H03L7/14 , H03L7/18 , H03L2207/50
Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.
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公开(公告)号：US09866180B2
公开(公告)日：2018-01-09
申请号：US14707846
申请日：2015-05-08
Inventor： John Paul Lesso , Emmanuel Philippe Christian Hardy
CPC classification number: H03F1/3241 , H03F1/3258 , H03F1/3264 , H03F3/183 , H03F2200/03 , H03F2201/3233 , H04R3/08 , H04R5/04 , H04R29/003 , H04R2420/03 , H04R2460/03
Abstract: This application relates to audio amplifier circuitry (100). An amplifier module (103) is located in a signal path between an input (101) and an output (102). A detection module (106) is configured to detect a characteristic of a load (104) electrically coupled, in use, to the output. A distortion setting controller (107) is provided for selecting one of a plurality of stored distortion settings {pi} based on the detected characteristic of the load; and a pre-distortion module (105) is configured to apply a first transfer function to a signal in the signal path prior to said amplifier module. The first transfer function is based on the selected distortion setting and for at least one of the stored distortion settings the corresponding first transfer function comprises a non-linear distortion function.
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公开(公告)号：US09748971B2
公开(公告)日：2017-08-29
申请号：US15243305
申请日：2016-08-22
Inventor： John Paul Lesso , Emmanuel Philippe Christian Hardy
CPC classification number: H03M7/30 , H03K7/08 , H03K9/08 , H03M1/18 , H03M1/181 , H03M1/50 , H03M1/504 , H03M3/484 , H03M2201/00
Abstract: This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
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Patent Agency Ranking
公开(公告)号：US09425813B2
公开(公告)日：2016-08-23
申请号：US14931332
申请日：2015-11-03
Inventor： John Paul Lesso , Emmanuel Philippe Christian Hardy
CPC classification number: H03M7/30 , H03K7/08 , H03K9/08 , H03M1/18 , H03M1/181 , H03M1/50 , H03M1/504 , H03M3/484 , H03M2201/00
Abstract: This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).
Abstract translation: 本申请涉及模拟 - 数字转换器（ADC）。 ADC200具有第一转换器（201），用于接收模拟输入信号（AIN），并输出诸如脉冲宽度调制（PWM）信号的时间编码信号（DT），其基于输入信号和第一转换 增益设置（GIN）。 在一些实施例中，第一转换器具有用于产生PWM信号的PWM调制器（401），使得输入信号由可在时间上连续变化的脉冲宽度编码。 第二转换器（202）接收时间编码信号并基于时间编码信号（DT）和第二转换增益设置（GO）输出数字输出信号（DOUT）。 第二转换器可以具有第一PWM到数字调制器（403）。 增益分配块（204）基于时间编码信号（DT）生成第一和第二转换增益设置。 增益分配块（204）可以具有第二PWM到数字调制器（203），其可以具有第一PWM到数字调制器（403）的较低等待时间和/或更低的分辨率。
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公开(公告)号：US12184281B2
公开(公告)日：2024-12-31
申请号：US18478572
申请日：2023-09-29
Inventor： John Laurence Pennock , John Paul Lesso
IPC: H03K19/0948 , H03K17/16 , H03K19/003 , H03M1/00
Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.
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公开(公告)号：US12178134B2
公开(公告)日：2024-12-24
申请号：US17172564
申请日：2021-02-10
Inventor： John Paul Lesso , Claire Motion
IPC: H10N30/80 , G01S7/527 , G01S15/931 , H10N30/30
Abstract: Circuitry for driving a transducer for an object detection system, the circuitry comprising drive circuitry configured to generate a drive waveform for the transducer, current monitor circuitry for monitoring a current through the transducer, and system identification circuitry. The system identification circuitry is configured to determine a characteristic of the transducer based on a first signal indicative of a drive voltage for the transducer and a second signal indicative of the current through the transducer. The circuitry is operative to adjust the drive waveform based on the determined characteristic of the transducer.
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公开(公告)号：US12131251B2
公开(公告)日：2024-10-29
申请号：US16358278
申请日：2019-03-19
Inventor： Anthony Magrath , John Paul Lesso
Abstract: The present disclosure relates to a neuron for an artificial neural network, the neuron comprising: a first dot product engine and a second dot product engine. The first dot product engine is operative to: receive a first set of weights; receive a set of inputs; and calculate the dot product of the set of inputs and the first set of weights to generate a first dot product engine output. The second dot product engine is operative to: receive a second set of weights; receive the set of inputs; and calculate the dot product of the set of inputs and the second set of weights to generate a second dot product engine output. The neuron further comprises a combiner operative to combine the first dot product engine output and the second dot product engine output to generate a combined output, and an activation function module arranged to apply an activation function to the combined output to generate a neuron output.
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公开(公告)号：US12053798B2
公开(公告)日：2024-08-06
申请号：US17102002
申请日：2020-11-23
Inventor： John Paul Lesso
IPC: B06B1/02 , H03K17/687 , H10N30/20
CPC classification number: B06B1/0207 , H03K17/6871 , B06B2201/55 , H03K2217/0081 , H10N30/20
Abstract: Drive circuitry for driving a piezoelectric transducer, the circuitry comprising: an inductor; a first reservoir capacitor; a switch network; and control circuitry configured to control operation of the switch network to selectively couple the inductor to one of a power supply, the first reservoir capacitor and the piezoelectric transducer, wherein the circuitry is operative in a discontinuous mode to transfer charge between the reservoir capacitor and the piezoelectric transducer, and wherein a polarity of the first reservoir capacitor is opposite to a polarity of the power supply.
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