公开(公告)号：US20060035450A1

公开(公告)日：2006-02-16

申请号：US10917055

申请日：2004-08-12

申请人： Martin Frank ,  Alexander Reznicek ,  Evgeni Gousev ,  Eduard Cartier

发明人： Martin Frank ,  Alexander Reznicek ,  Evgeni Gousev ,  Eduard Cartier

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/495 ,  H01L21/76254 ,  H01L21/823828 ,  H01L29/517

摘要： A method of forming a gate stack for semiconductor electronic devices utilizing wafer bonding of at least one structure containing a high-k dielectric material is provided. The method of the present invention includes a step of first selecting a first and second structure having a major surface respectively. In accordance with the present invention, at least one, or both, of the first and second structures includes at least a high-k dielectric material. Next, the major surfaces of the first and second structures are bonded together to provide a bonded structure containing at least the high-k dielectric material of a gate stack.

摘要翻译： 提供了一种利用至少一种包含高介电材料的结构的晶片接合形成用于半导体电子器件的栅叠层的方法。 本发明的方法包括分别首先选择具有主表面的第一和第二结构的步骤。 根据本发明，第一和第二结构中的至少一个或两者包括至少一个高k电介质材料。 接下来，将第一和第二结构的主表面结合在一起，以提供至少包含栅叠层的高k电介质材料的键合结构。

公开(公告)号：US20050269634A1

公开(公告)日：2005-12-08

申请号：US10863830

申请日：2004-06-04

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20050064690A1

公开(公告)日：2005-03-24

申请号：US10605261

申请日：2003-09-18

申请人： Ricky Amos ,  Douglas Buchanan ,  Cyril Cabral ,  Evgeni Gousev ,  Victor Ku ,  An Steegen

发明人： Ricky Amos ,  Douglas Buchanan ,  Cyril Cabral ,  Evgeni Gousev ,  Victor Ku ,  An Steegen

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/76895 ,  H01L21/823835

摘要： Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds. A second silicide may be employed within the gate. A replacement gate is made from two different metals (dual metal gate replacement) prior to capping with a silicide.

摘要翻译： 硅化物通过不同的工艺选择被引入到CMOS器件的栅极区域，用于常规和替代栅极类型工艺。 将硅化物放置在栅极本身中，引入硅化物直接与栅极电介质接触，将硅化物作为填充物引入金属栅极顶部，并准备就绪，并将硅化物作为覆盖层引入到多晶硅上或 现有的金属门。 硅化物用作连接CMOS结构的PFET和NFET器件的选项。 该过程保护金属栅极，同时允许源极和漏极硅化物与栅极硅化物不同的硅化物。 提供了具有栅极和源极和漏极区域的半导体衬底。 栅极电介质层与金属栅极层一起沉积在衬底上。 然后用形成在栅极顶部上的硅化物对金属栅极层进行封装，然后继续进行常规的器件形成。 可以在栅极内使用第二硅化物。 在使用硅化物封盖之前，更换栅极由两种不同的金属（双金属栅极替代）制成。

公开(公告)号：US07887711B2

公开(公告)日：2011-02-15

申请号：US10170914

申请日：2002-06-13

申请人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Evgeni Gousev ,  Harald Okorn-Schmidt ,  Katherine L. Saenger

发明人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Evgeni Gousev ,  Harald Okorn-Schmidt ,  Katherine L. Saenger

IPC分类号： B44C1/22 ,  H01L21/00

CPC分类号： H01L21/31122 ,  Y10S438/924

摘要： A system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an energetic particle bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. Besides using the ion implantation damage (I/I damage) plus wet etch technique to metal oxides (including metal oxides not previously etchable by wet methods), other damage methods including lower energy, plasma-based ion bombardment, may be implemented. Plasma-based ion bombardment typically uses simpler and cheaper tooling, and results in less collateral damage to underlying structures as the damage profile can be more easily localized to the depth of the thin metal oxide film.

摘要翻译： 一种在半导体结构中图案化金属氧化物材料的系统和方法。 该方法包括在衬底上沉积金属氧化物材料层的第一步骤。 然后，在金属氧化物层之上形成图案化掩模层，留下暴露金属氧化物层的一个或多个第一区域。 接着对金属氧化物层的暴露的第一区域进行高能粒子轰击处理，从而破坏金属氧化物层的第一区域。 然后通过化学蚀刻去除金属氧化物层的暴露和损坏的第一区域。 有利地，该系统和方法被实现以在小规模半导体器件中提供高k电介质材料。 除了使用离子注入损伤（I / I损伤）以及湿法蚀刻技术对金属氧化物（包括以前不能用湿法蚀刻的金属氧化物）外，还可以实施包括较低能量，基于等离子体的离子轰击等其他损伤方法。 基于等离子体的离子轰击通常使用更简单和更便宜的工具，并且导致对下面的结构的较少的附带损伤，因为损伤分布可以更容易地定位于薄金属氧化物膜的深度。

公开(公告)号：US20100206629A1

公开(公告)日：2010-08-19

申请号：US12371302

申请日：2009-02-13

申请人： Bangalore R. Natarajan ,  Evgeni Gousev ,  Kristopher A. Lavery

发明人： Bangalore R. Natarajan ,  Evgeni Gousev ,  Kristopher A. Lavery

IPC分类号： H05K5/00 ,  B32B37/00 ,  B32B38/00 ,  B32B9/00 ,  B32B17/00 ,  B05D1/02

CPC分类号： B01J20/2808 ,  B01D53/261 ,  B01D53/28 ,  B01D2253/108 ,  B01J20/18 ,  B01J20/183 ,  B01J20/2803 ,  B01J2220/42 ,  B81B2201/047 ,  B81C1/00285 ,  B81C2201/112 ,  H01L23/26 ,  H01L51/5259 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1433 ,  Y10T156/10 ,  H01L2924/00

摘要： Systems and methods for providing MEMS devices with integrated desiccant are provided. In one embodiment, a dry composition comprising desiccant is impact sprayed onto the backplate or substrate of a MEMS device, and becomes fused with the substrate. In another embodiment, the desiccant is impact sprayed such that the desiccant adheres to the impact sprayed surface. In yet another embodiment, the impact-sprayed surface is impregnated with the desiccant. In still another embodiment, the desiccant is combined with a suitable inorganic binder, then impact sprayed such that the desiccant adheres to the impact sprayed surface. In yet a further embodiment, the desiccant is micronized or pulverized into a powder of desired particle size, and then impact sprayed onto a surface. Thus, the desiccant particles or powder are fused onto the target surface through the impact spraying process.

摘要翻译： 提供了提供MEMS器件集成干燥剂的系统和方法。 在一个实施方案中，将包含干燥剂的干组合物冲击喷射到MEMS装置的背板或基板上，并与基底熔合。 在另一个实施方案中，干燥剂被冲击喷雾，使得干燥剂粘附到冲击喷涂表面上。 在另一个实施例中，冲击喷射表面用干燥剂浸渍。 在另一个实施方案中，将干燥剂与合适的无机粘合剂组合，然后冲洗喷雾，使得干燥剂粘附到冲击喷涂表面。 在又一个实施方案中，干燥剂被微粉化或粉碎成所需粒度的粉末，然后冲击喷涂到表面上。 因此，干燥剂颗粒或粉末通过冲击喷涂工艺熔合到目标表面上。

公开(公告)号：US07737050B2

公开(公告)日：2010-06-15

申请号：US11554097

申请日：2006-10-30

申请人： Edward Dennis Adams ,  Jay Sanford Burnham ,  Evgeni Gousev ,  James Spiros Nakos ,  Heather Elizabeth Preuss ,  Joseph Francis Shepard, Jr.

发明人： Edward Dennis Adams ,  Jay Sanford Burnham ,  Evgeni Gousev ,  James Spiros Nakos ,  Heather Elizabeth Preuss ,  Joseph Francis Shepard, Jr.

IPC分类号： H01L21/31 ,  H01L21/467

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/02337 ,  H01L21/28202 ,  H01L21/3144

摘要： A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.

摘要翻译： 形成氮化硅氧化物层的方法。 该方法包括：在硅衬底的表面上形成二氧化硅层; 在小于或等于约900℃的温度和大于约500托的压力下进行二氧化硅层的快速热氮化，以形成初始氮化氧化硅层; 并且在小于或等于约900℃的温度和大于约500托的压力下进行初始氮化硅氧化物层的快速热氧化或退火以形成氮化的氧化硅层。 还有一种形成具有氮化硅氧化物介电层的MOSFET的方法。

公开(公告)号：US07733552B2

公开(公告)日：2010-06-08

申请号：US11689430

申请日：2007-03-21

申请人： Ana R. Londergan ,  Bangalore R. Natarajan ,  Evgeni Gousev ,  James Randolph Webster ,  David Heald

发明人： Ana R. Londergan ,  Bangalore R. Natarajan ,  Evgeni Gousev ,  James Randolph Webster ,  David Heald

IPC分类号： G02F1/00

CPC分类号： G02B26/001 ,  B81B3/0008 ,  B81B2201/047

摘要： Devices, methods, and systems comprising a MEMS device, for example, an interferometric modulator, that comprises a cavity in which a layer coats multiple surfaces. The layer is conformal or non-conformal. In some embodiments, the layer is formed by atomic layer deposition (ALD). Preferably, the layer comprises a dielectric material. In some embodiments, the MEMS device also exhibits improved characteristics, such as improved electrical insulation between moving electrodes, reduced stiction, and/or improved mechanical properties.

摘要翻译： 包括MEMS器件（例如干涉式调制器）的器件，方法和系统，其包括其中层涂覆多个表面的空腔。 该层是保形的或非保形的。 在一些实施例中，该层由原子层沉积（ALD）形成。 优选地，该层包括电介质材料。 在一些实施例中，MEMS器件还表现出改进的特性，例如移动电极之间的改善的电绝缘性，降低的静摩擦力和/或改善的机械性能。

公开(公告)号：US07729036B2

公开(公告)日：2010-06-01

申请号：US11938673

申请日：2007-11-12

申请人： Daniel Felnhofer ,  Evgeni Gousev

发明人： Daniel Felnhofer ,  Evgeni Gousev

IPC分类号： G02B26/00 ,  G02B26/02

CPC分类号： B81B3/0086 ,  B81B2201/045 ,  G02B26/001 ,  G11C23/00

摘要： A capacitive MEMS device is formed having a material between electrodes that traps and retains charges. The material can be realized in several configurations. It can be a multilayer dielectric stack with regions of different band gap energies or band energy levels. The dielectric materials can be trappy itself, i.e. when defects or trap sites are pre-fabricated in the material. Another configuration involves a thin layer of a conductive material with the energy level in the forbidden gap of the dielectric layer. The device may be programmed (i.e. offset and threshold voltages pre-set) by a method making advantageous use of charge storage in the material, wherein the interferometric modulator is pre-charged in such a way that the hysteresis curve shifts, and the actuation voltage threshold of the modulator is significantly lowered. During programming phase, charge transfer between the electrodes and the materials can be performed by applying voltage to the electrodes (i.e. applying electrical field across the material) or by UV-illumination and injection of electrical charges over the energy barrier. The interferometric modulator may then be retained in an actuated state with a significantly lower actuation voltage, thereby saving power.

摘要翻译： 形成电容MEMS器件，其具有陷阱并保持电荷的电极之间的材料。 该材料可以在几种配置中实现。 它可以是具有不同带隙能量或带能级的区域的多层电介质叠层。 电介质材料本身可以是歪斜的，即当在材料中预先制造缺陷或捕获位置时。 另一种结构涉及导电材料的薄层，其中电介质层的禁止间隙具有能级。 可以通过有利地使用材料中的电荷存储的方法来对器件进行编程（即，偏移和阈值电压预设），其中干涉式调制器以滞后曲线偏移的方式预充电，并且致动电压 调制器的阈值显着降低。 在编程阶段期间，电极和材料之间的电荷转移可以通过向电极施加电压（即跨越材料施加电场）或通过UV照射和在能量屏障上注入电荷来执行。 然后干涉式调制器可以以明显更低的致动电压保持在致动状态，从而节省功率。

公开(公告)号：US07688494B2

公开(公告)日：2010-03-30

申请号：US12115395

申请日：2008-05-05

申请人： Gang Xu ,  Evgeni Gousev

发明人： Gang Xu ,  Evgeni Gousev

IPC分类号： G02F1/03 ,  G02B26/00

CPC分类号： G02B26/001 ,  B81B2201/047 ,  B81C1/00246

摘要： A microelectromechanical (MEMS) device is presented which comprises a metallized semiconductor. The metallized semiconductor can be used for conductor applications because of its low resistivity, and for transistor applications because of its semiconductor properties. In addition, the metallized semiconductor can be tuned to have optical properties which allow it to be useful for optical MEMS devices.

摘要翻译： 提出了一种包括金属化半导体的微机电（MEMS）器件。 金属化半导体由于其低电阻率而可用于导体应用，并且由于其半导体性质而可用于晶体管应用。 此外，金属化半导体可以被调谐以具有允许其对于光学MEMS器件有用的光学性质。

公开(公告)号：US20090002804A1

公开(公告)日：2009-01-01

申请号：US12163660

申请日：2008-06-27

申请人： Bangalore R. Natarajan ,  Kasra Khazeni ,  David Heald ,  Rihui He ,  Sriram Akella ,  Evgeni Gousev

发明人： Bangalore R. Natarajan ,  Kasra Khazeni ,  David Heald ,  Rihui He ,  Sriram Akella ,  Evgeni Gousev

IPC分类号： G02B26/00 ,  H01L21/00

CPC分类号： B81C1/0092 ,  B81B3/0005 ,  B81B2201/047 ,  B81C2201/112 ,  G02B26/001

摘要： Methods, devices, and systems provide MEMS devices exhibiting at least one of reduced stiction, reduced hydrophilicity, or reduced variability of certain electrical characteristics using MEMS devices treated with water vapor. The treatment is believed to form one or more passivated surfaces on the interior and/or exterior of the MEMS devices. Relatively gentle temperature and pressure conditions ensure modification of surface chemistry without excessive water absorption after removal of sacrificial material to release the MEMS devices.

摘要翻译： 方法，装置和系统提供使用用水蒸汽处理的MEMS装置展现降低的静摩擦，降低的亲水性或某些电气特性的变化性中的至少一个的MEMS装置。 认为处理在MEMS器件的内部和/或外部形成一个或多个钝化表面。 相对温和的温度和压力条件确保在去除牺牲材料以释放MEMS器件之后，不改变表面化学性质而不过度吸水。