公开(公告)号：US07170181B2

公开(公告)日：2007-01-30

申请号：US10707064

申请日：2003-11-19

申请人： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Wolfgang Sauter ,  Barbara A. Waterhouse

发明人： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Wolfgang Sauter ,  Barbara A. Waterhouse

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

摘要： An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the full metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.

摘要翻译： RF结构包括用于引线键合的最佳焊盘和包含相对较厚的金属电感器导线的高性能电感器，两者都位于互连结构的最终互连级别的顶部。 具体地，RF结构包括具有第一厚度的金属电感器线和位于其表面上的具有第二厚度的主要面积的金属接合焊盘的电介质层，其中第一厚度大于第二厚度。 在本发明的RF结构中，大部分金属焊盘被减薄以进行引线接合，同时保持结构的其它区域中的全部金属线厚度用于电感器性能要求，例如低电阻率。 还提供了制造上述RF结构的方法。

公开(公告)号：US07410894B2

公开(公告)日：2008-08-12

申请号：US11161217

申请日：2005-07-27

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John E. Florkey ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John E. Florkey ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/44 ,  H01L21/20 ,  H01L29/00

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

摘要翻译： 一种形成半导体结构的方法以及如此形成的半导体结构，其中诸如电感器的传输线形成在最后一个金属布线层的表面上方的平面上。

公开(公告)号：US20080258197A1

公开(公告)日：2008-10-23

申请号：US11737844

申请日：2007-04-20

申请人： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Robert M. Rassel ,  Richard J. Rassel ,  Stephen A. St Onge

发明人： Douglas D. Coolbaugh ,  Zhong-Xiang He ,  Robert M. Rassel ,  Richard J. Rassel ,  Stephen A. St Onge

IPC分类号： H01L21/20 ,  H01L29/04

CPC分类号： H01L29/94

摘要： A semiconductor-insulator-silicide (SIS) capacitor is formed by depositing a thin silicon containing layer on a salicide mask dielectric layer, followed by lithographic patterning of the stack and metallization of the thin silicon containing layer and other exposed semiconductor portions of a semiconductor substrate. The thin silicon containing layer is fully reacted during metallization and consequently converted to a silicide alloy layer, which is a first electrode of a capacitor. The salicide mask dielectric layer is the capacitor dielectric. The second electrode of the capacitor may be a doped polycrystalline silicon containing layer, a doped single crystalline semiconductor region, or another doped polycrystalline silicon containing layer disposed on the doped polycrystalline silicon containing layer. The SIS insulator may further comprise other dielectric layers and conductive layers to increase capacitance per area.

摘要翻译： 半导体绝缘体硅化物（SIS）电容器通过在硅化物掩模介电层上沉积薄硅层而形成，随后叠层的平版印刷图案化以及薄硅层和半导体衬底的其它暴露的半导体部分的金属化 。 含硅薄层在金属化期间完全反应，因此转化为硅化物合金层，其是电容器的第一电极。 硅化物掩模介电层是电容器电介质。 电容器的第二电极可以是掺杂的多晶硅含硅层，掺杂的单晶半导体区域或设置在掺杂的多晶硅含硅层上的另一掺杂的多晶硅含硅层。 SIS绝缘体还可以包括其它电介质层和导电层，以增加每面积的电容。

公开(公告)号：US07399696B2

公开(公告)日：2008-07-15

申请号：US11161415

申请日：2005-08-02

申请人： Douglas D. Coolbaugh ,  Mete Erturk ,  Zhong-Xiang He ,  Anthony K. Stamper

发明人： Douglas D. Coolbaugh ,  Mete Erturk ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC分类号： H01L21/4763

CPC分类号： H01L23/5227 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a high performance inductor comprises providing a substrate; forming a plurality of wiring levels over the substrate, wherein each of the wiring levels comprise a dielectric layer; forming a first trench having a first depth in a first dielectric layer on a first wiring level; forming a second trench in the first dielectric layer having a second depth extending at least into a second wiring level; forming a conductor layer substantially simultaneously in the first and second trenches; and removing portions of the conductor layer overfilling the first and second trenches to form a spiral-shaped inductor in the second trench. The method may further comprise forming an interconnect structure in the first trench.

摘要翻译： 形成高性能电感器的方法包括：提供衬底; 在衬底上形成多个布线层，其中每个布线层包括介电层; 在第一布线层上形成在第一介电层中具有第一深度的第一沟槽; 在所述第一介电层中形成具有至少延伸至第二布线层的第二深度的第二沟槽; 在第一和第二沟槽中基本上同时地形成导体层; 以及去除超过第一和第二沟槽的导体层的部分，以在第二沟槽中形成螺旋形电感器。 该方法还可以包括在第一沟槽中形成互连结构。

公开(公告)号：US20090106726A1

公开(公告)日：2009-04-23

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20080122096A1

公开(公告)日：2008-05-29

申请号：US11460314

申请日：2006-07-27

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US07904868B2

公开(公告)日：2011-03-08

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US07701015B2

公开(公告)日：2010-04-20

申请号：US10596573

申请日：2003-12-16

申请人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

发明人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

IPC分类号： H01L29/72

CPC分类号： H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

摘要翻译： 公开了一种集成电路结构的方法和结构，其包括多个互补金属氧化物半导体（CMOS）晶体管和位于单个衬底上的多个垂直双极晶体管。 垂直双极晶体管比CMOS晶体管更高的器件。 在该结构中，钝化层位于衬底上方，并且位于垂直双极晶体管和CMOS晶体管之间。 布线层位于钝化层的上方。 垂直双极晶体管与布线层直接接触，并且CMOS晶体管通过延伸穿过钝化层的触点连接到布线层。

公开(公告)号：US20080308940A1

公开(公告)日：2008-12-18

申请号：US12198196

申请日：2008-08-26

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L23/522

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20090039522A1

公开(公告)日：2009-02-12

申请号：US10596573

申请日：2003-12-16

申请人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

发明人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

IPC分类号： H01L23/52

CPC分类号： H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

摘要翻译： 公开了一种集成电路结构的方法和结构，其包括多个互补金属氧化物半导体（CMOS）晶体管和位于单个衬底上的多个垂直双极晶体管。 垂直双极晶体管比CMOS晶体管更高的器件。 在该结构中，钝化层位于衬底上方，并且位于垂直双极晶体管和CMOS晶体管之间。 布线层位于钝化层的上方。 垂直双极晶体管与布线层直接接触，并且CMOS晶体管通过延伸穿过钝化层的触点连接到布线层。