公开(公告)号：US5585663A

公开(公告)日：1996-12-17

申请号：US511565

申请日：1995-08-04

申请人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/82 ,  H01L23/367 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/3672 ,  H01L2924/0002 ,  Y10S438/922

摘要： An electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.

摘要翻译： 埋在石英下的电可编程熔丝和具有特定结构的聚酰亚胺层，以增强其“热”能力。 保险丝设计为“吹”并快速冷却，以免对保险丝上方和周围的区域造成损坏。 保险丝上方加上钝化层，作为散热片，吸收并重新分配从一个局部区域产生的热量到较宽和较冷的区域。 用于保险丝和散热器的材料被选择为与氧化物和聚酰亚胺个性化方案兼容。 保险丝的建模可以优化保险丝的特性，特别是在保险丝编程期间向钝化层的表面传输热波。

公开(公告)号：US5444287A

公开(公告)日：1995-08-22

申请号：US292901

申请日：1994-08-10

申请人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01H85/00 ,  H01H85/02 ,  H01H85/046 ,  H01H85/12 ,  H01L23/525 ,  H01L23/58 ,  H01L29/167 ,  H01L23/48 ,  H01L29/207

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： A noise immune fuse having sub-micron dimensions which can be programmed by an electrically and thermally synchronized event. The fuse includes a pair of fuse links in close proximity of each other, a layer of thermally conductive and electrically insulating material thermally coupling the two links forming the pair, and means for programming the first link by prompting the second link to gate the energy transfer between the links via the coupling layer. By combining thermal and electrical pulses to perform the programming function, the reliability of the fuse structure is greatly enhanced when compared to that of a single element fuse.

摘要翻译： 具有亚微米尺寸的噪声免疫保险丝，可通过电和热同步事件进行编程。 熔丝包括彼此紧密相邻的一对熔丝链，热耦合形成该对的两个连接的导热和电绝缘材料层，以及用于通过提示第二连接件对能量传递进行栅极编程的装置 通过耦合层在链路之间。 通过组合热和电脉冲来执行编程功能，与单个元件熔断器相比，熔丝结构的可靠性大大提高。

公开(公告)号：US5298784A

公开(公告)日：1994-03-29

申请号：US858835

申请日：1992-03-27

申请人： Jeffrey P. Gambino ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Jeffrey P. Gambino ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L23/48

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002

摘要： An improved antifuse uses metal penetration of either a P-N diode junction or a Schottky diode. The P-N junction, or Schottky diode, is contacted by a diffusion barrier such as TiN, W, Ti-W alloy, or layers of Ti and Cr, with a metal such as Al. Al-CU alloy, Cu, Au, or Ag on top of the diffusion barrier. When this junction is stressed with voltage pulse producing a high current density, severe joule heating occurs resulting in metal penetration of the diffusion barrier and the junction. The voltage drop across the junction decreases by about a factor of ten after the current stress and is stable thereafter. Alternatively, a shallow P-N junction in a silicon substrate is contacted by a layer of metal that forms a silicide, such as Ti, Cr, W, Mo, or Ta. Stressing the junction with a voltage pulse to produce a high current density results in the metal penetrating the junction and reacting with the substrate to form a silicide.

摘要翻译： 改进的反熔丝使用P-N二极管结或肖特基二极管的金属穿透。 P-N结或肖特基二极管通过诸如TiN，W，Ti-W合金或Ti和Cr的层的扩散阻挡层与诸如Al的金属接触。 Al-Cu合金，Cu，Au或Ag在扩散阻挡层的顶部。 当该结被电压脉冲施加而产生高电流密度时，发生严重的焦耳加热，导致扩散阻挡层和结的金属穿透。 跨接点的电压降在电流应力之后减少约十倍，此后稳定。 或者，硅衬底中的浅P-N结与由Ti，Cr，W，Mo或Ta形成硅化物的金属层接触。 用电压脉冲强加结以产生高电流密度导致金属穿透接合部并与衬底反应形成硅化物。

公开(公告)号：US5213249A

公开(公告)日：1993-05-25

申请号：US890988

申请日：1992-05-29

申请人： David C. Long ,  Krishna Seshan

发明人： David C. Long ,  Krishna Seshan

IPC分类号： B23K20/10 ,  H01L21/00

CPC分类号： H01L21/67253 ,  B23K20/10 ,  H01L24/75 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/78 ,  H01L2224/85205 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/15787

摘要： An ultrasonic adhesion/dehesion monitoring apparatus for monitoring the adhesion/dehesion between first and second substrates comprising: a. an ultrasonic source for transmitting ultrasonic energy to at least first and second substrates; b. means for measuring the instantaneous AC current and instantaneous AC supplied to said ultrasonic source; c. means for multiplying the instantaneous AC voltage and the instantaneous AC current to determine the instantaneous power supplied to said ultrasonic source; and d. monitor means coupled to said ultrasonic source and said power determining means for monitoring the instantaneous power supplied to said ultrasonic source. Also disclosed is a method for monitoring the quality and/or adhesion/dehesion between first and second substrates in the ultrasonic adhesion/dehesion monitoring apparatus.

摘要翻译： 一种用于监测第一和第二基底之间的粘合/粘合的超声粘附/粘合监测装置，包括：a。 用于将超声波能量传输到至少第一和第二基底的超声波源; b。 用于测量提供给所述超声波源的瞬时AC电流和瞬时AC的装置; C。 用于将瞬时AC电压和瞬时AC电流相乘以确定提供给所述超声波源的瞬时功率的装置; 和d。 监视器装置，耦合到所述超声波源和所述功率确定装置，用于监视提供给所述超声波源的瞬时功率。 还公开了一种用于在超声波粘合/粘合监测装置中监测第一和第二基板之间的质量和/或粘附/粘合的方法。

公开(公告)号：US4962294A

公开(公告)日：1990-10-09

申请号：US322955

申请日：1989-03-14

申请人： Keith F. Beckham ,  David C. Challener ,  Arunava Gupta ,  Joseph M. Harvilchuck ,  James M. Leas ,  James R. Lloyd ,  David C. Long ,  Horatio Quinones ,  Krishna Seshan ,  Morris Shatzkes

发明人： Keith F. Beckham ,  David C. Challener ,  Arunava Gupta ,  Joseph M. Harvilchuck ,  James M. Leas ,  James R. Lloyd ,  David C. Long ,  Horatio Quinones ,  Krishna Seshan ,  Morris Shatzkes

IPC分类号： B23K26/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525 ,  H05K3/22

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A method for causing an open circuit in an electrical conductor is provided, including the steps of: conducting a direct current through the conductor; and applying heat at a selected location on the conductor whereat it is desired to cause the open circuit of the conductor.

公开(公告)号：US07411269B2

公开(公告)日：2008-08-12

申请号：US11091967

申请日：2005-03-28

申请人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

发明人： Qing Ma ,  Jin Lee ,  Harry Fujimoto ,  Changhong Dai ,  Shiuh-Wuu Lee ,  Travis Eiles ,  Krishna Seshan

IPC分类号： H01L29/72

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/7846 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

公开(公告)号：US07262070B2

公开(公告)日：2007-08-28

申请号：US10675587

申请日：2003-09-29

申请人： Theodore Doros ,  Krishna Seshan

发明人： Theodore Doros ,  Krishna Seshan

IPC分类号： H01L21/00

CPC分类号： B81B3/0072 ,  B81C2201/0109

摘要： Embodiments of the present invention form a weight-compensating/tuning layer on a structure (e.g., a silicon wafer with one or more layers of material (e.g., films)) having variations in its surface topology. The variations in surface topology take the form of thick and thin regions of materials. The weight-compensating/tuning layer includes narrow and wide regions corresponding to the thick and thin regions, respectively.

摘要翻译： 本发明的实施例在其表面拓扑变化的结构（例如，具有一层或多层材料的硅晶片（例如膜））上形成体重补偿/调谐层。 表面拓扑的变化采取厚薄的材料区域的形式。 重量补偿/调谐层分别包括对应于厚和薄区域的窄且宽的区域。

公开(公告)号：US20070139140A1

公开(公告)日：2007-06-21

申请号：US11314361

申请日：2005-12-20

申请人： Valluri Rao ,  Theodore Doros ,  Qing Ma ,  Krishna Seshan ,  Li-Peng Wang

发明人： Valluri Rao ,  Theodore Doros ,  Qing Ma ,  Krishna Seshan ,  Li-Peng Wang

IPC分类号： H03H9/58

CPC分类号： H03H3/04 ,  H03H3/0076 ,  H03H2003/0428 ,  H03H2003/0478

摘要： Multiple FBARs may be manufactured on a single wafer and later diced. Ideally, all devices formed in a wafer would have the same resonance frequency. However, due to manufacturing variances, the frequency response of the FBAR devices may vary slightly across the wafer. An RF map may be created to determine zones over the wafer where FBARs in that zone all vary from a target frequency by a similar degree. A tuning layer may be deposited over the wafer. Lithographically patterned features to the tuning layer based on the zones identified by the RF map may be used to correct the FBARs to a target resonance frequency with the FBARs still intact on the wafer.

摘要翻译： 多个FBAR可以在单个晶片上制造并且稍后被切割。 理想地，形成在晶片中的所有器件将具有相同的谐振频率。 然而，由于制造方差，FBAR器件的频率响应可能会在晶圆上略有不同。 可以创建RF映射以确定晶片上的区域，其中该区域中的FBAR全部从目标频率变化相似程度。 调谐层可以沉积在晶片上。 可以使用基于由RF映射表示的区域的调谐层的光刻图案特征来将FBAR校正到目标谐振频率，同时FBAR在晶片上仍然完整。

公开(公告)号：US07034402B1

公开(公告)日：2006-04-25

申请号：US09606319

申请日：2000-06-28

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05578 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/00

摘要： The present invention discloses a novel layout and process for a device with segmented BLM for the I/Os. In a first embodiment, each BLM is split into two segments. The segments are close to each other and connected to the same overlying bump. In a second embodiment, each BLM is split into more than two segments. In a third embodiment, each segment is electrically connected to more than one underlying via. In a fourth embodiment, each segment is electrically connected to more than one underlying bond pad.

摘要翻译： 本发明公开了一种用于I / O的具有分段BLM的设备的新颖布局和过程。 在第一实施例中，每个BLM被分成两个段。 这些片段彼此靠近并连接到相同的上覆凸起。 在第二实施例中，每个BLM被分成多于两个段。 在第三实施例中，每个段电连接到多于一个的底层通孔。 在第四实施例中，每个段电连接到多于一个的底层接合焊盘。

公开(公告)号：US20060033211A1

公开(公告)日：2006-02-16

申请号：US11203849

申请日：2005-08-15

申请人： Krishna Seshan

发明人： Krishna Seshan

IPC分类号： H01L23/48

CPC分类号： H01L24/02 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H01L2924/00

摘要： An electrical device includes electrical contact pads, a supply voltage bus and an interconnection circuit. The electrical contact pads receive a supply voltage, and the bus is electrically connected to the electrical contact pads. For each electrical contact pad, the interconnection circuit forms a redundant connection between the bus and the electrical contact pad. The electrical device may include a passivation layer that includes windows to establish electrical contact between the electrical contact pads and the supply voltage bus. This window may be elongated in a path that is generally aligned with the path along which the supply voltage bus extends.