公开(公告)号：US06876562B2

公开(公告)日：2005-04-05

申请号：US10273869

申请日：2002-10-17

申请人： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

发明人： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

IPC分类号： G11C5/00 ,  H05K1/18 ,  G11C5/06

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

公开(公告)号：US06678205B2

公开(公告)日：2004-01-13

申请号：US10036141

申请日：2001-12-26

申请人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

发明人： Brian Johnson ,  Brent Keeth ,  Jeffrey W. Janzen ,  Troy A. Manning ,  Chris G. Martin

IPC分类号： G11C800

CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal, control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端，并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号，该设备中的控制电路响应于 施加到设备的异步输入终端的预定的异步信号序列，以将设备置于其中禁用内部时钟电路的替代操作模式，使得可以使用具有频率的外部时钟信号在替代模式下操作该设备 小于预定的最小频率。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

公开(公告)号：US06445643B2

公开(公告)日：2002-09-03

申请号：US09745608

申请日：2000-12-20

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

摘要： A method of setting write latency and a write/valid indicator circuit for use with the method. In a preferred embodiment, time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. The write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

摘要翻译： 设置写延迟的方法和用于该方法的写/有效指示器电路。 在优选实施例中，时间裕度区域刚好在第一或前沿之后并且刚好在时钟信号的前导码的第二或后续边缘之前建立，使得等待时间设置将被发现是不可接受的，如果它使得写使能信号转变 在这两个地区。 写入/有效指示电路通过延迟时钟信号或写入使能信号并将它们的定时与未延时写入使能信号或时钟信号的定时进行比较来创建起始和结束时间裕度区域。

公开(公告)号：US06333893B1

公开(公告)日：2001-12-25

申请号：US09642090

申请日：2000-08-21

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： A method and apparatus that expands the data envelope of captured data to a predetermined number of clocks cycles. The predetermined number of clock cycles is large enough to ensure that an internally generated master clock edge remains within the data envelope over the entire operating range. This way, captured data remains valid and can be properly transferred to the master clock domain from a capture clock domain despite temperature and voltage variations that may effect the timing of the memory device.

摘要翻译： 一种将捕获数据的数据包络扩展到预定数量的时钟周期的方法和装置。 预定数量的时钟周期足够大，以确保内部产生的主时钟沿在整个工作范围内保持在数据包络内。 这样，捕获的数据保持有效，并且可以从捕获时钟域正确地传送到主时钟域，尽管可能影响存储器件的时序的温度和电压变化。

公开(公告)号：US20050185498A1

公开(公告)日：2005-08-25

申请号：US11059645

申请日：2005-02-17

申请人： Brent Keeth ,  Brian Johnson ,  Terry Lee ,  Paul Fuller

发明人： Brent Keeth ,  Brian Johnson ,  Terry Lee ,  Paul Fuller

IPC分类号： G11B27/00 ,  G11C7/10 ,  G11C8/02 ,  H03L7/081 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C2207/2254 ,  H03L7/0812 ,  H04L7/0041 ,  H04L7/043 ,  H04L7/10

摘要： Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2N bit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.

摘要翻译： 公开了一种用于SLDRAM存储器件的改进的启动/复位校准装置和方法，基于伪随机序列的二进制位校准模式用于校准数据的相对定时 和锁存时钟信号，以确保存储器件的最佳操作。 另外，在一个数据通路的校准过程中，其他附近的数据路径可能同步，异相和/或校正模式的相位和异相版本同时接收和/或同时接收，从而在更多的条件下校准校准数据路径 近似随机运行条件。

公开(公告)号：US20050122814A1

公开(公告)日：2005-06-09

申请号：US11030844

申请日：2005-01-07

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

公开(公告)号：US06882579B2

公开(公告)日：2005-04-19

申请号：US10705388

申请日：2003-11-10

申请人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy A. Manning

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US06851016B2

公开(公告)日：2005-02-01

申请号：US10720183

申请日：2003-11-25

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

摘要翻译： 在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。 本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统 读延迟。

公开(公告)号：US20050007806A1

公开(公告)日：2005-01-13

申请号：US10910979

申请日：2004-08-03

申请人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

发明人： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC分类号： G11C5/00 ,  H05K1/18 ,  G11C7/00

CPC分类号： H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

摘要： The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

摘要翻译： 本发明涉及一种用于形成微电子存储器件的系统，模块以及装置和方法。 在一个实施例中，系统包括处理器和耦合到处理器的控制器，其中至少一个存储器模块耦合到控制器，该模块包括一对存储器件，其相对地定位在衬底的相应表面上并且通过延伸穿过 耦合器件的端子的基板，所述端子被选择为包括被配置为传送功能兼容的信号的一组端子。

公开(公告)号：US06807613B1

公开(公告)日：2004-10-19

申请号：US09641516

申请日：2000-08-21

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： G06F1206

CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/24 ,  G11C8/20 ,  G11C11/4076 ,  G11C11/4078 ,  G11C16/22

摘要： Some synchronous semiconductor memory devices accept a command clock which is buffered and a write clock which is unbuffered. Write command are synchronized to the command clock while the associated write data is synchronized to the write clock. Due to the use of the buffer, an arbitrary phase shift can exist between the command and write clocks. The presence of the phase shift between the two clocks makes it difficult to determine when a memory device should accept write data associated a write command. A synchronous memory device in accordance with the present invention utilizes the unbuffered strobe signal which is normally tristated during writes as a flag to mark the start of write data. A preamble signal may be asserted on the strobe signal line prior to asserting the flag signal in order to simplify flag detection.

摘要翻译： 一些同步半导体存储器件接受缓冲的命令时钟和不缓冲的写时钟。 写命令与命令时钟同步，而相关的写数据与写时钟同步。 由于使用缓冲器，在命令和写时钟之间可能存在任意的相移。 两个时钟之间的相移的存在使得难以确定存储器件何时应该接受与写入命令相关联的写入数据。 根据本发明的同步存储器件利用在写入期间正常三态的无缓冲选通信号作为标记写数据开始的标志。 在断言标志信号之前，可以在选通信号线上断言前导信号，以简化标志检测。