公开(公告)号：US20120306043A1

公开(公告)日：2012-12-06

申请号：US13534854

申请日：2012-06-27

申请人： Ji Pan ,  Anup Bhalla

发明人： Ji Pan ,  Anup Bhalla

IPC分类号： H01L29/47

CPC分类号： H01L29/66727 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/782

摘要： A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.

摘要翻译： 肖特基二极管包括肖特基势垒和设置在肖特基势垒附近的多个掺杂区，作为浮岛，用作用于防止从反向电压产生的漏电流的PN结。 在其中设置有肖特基势垒材料的半导体衬底中开放的至少一个沟槽构成肖特基势垒。 肖特基势垒材料也可以设置在用于构成肖特基势垒的沟槽的侧壁上。 沟槽可以填充由设置在其中的用于构成肖特基势垒的Ti / TiN或其中的钨金属组成的肖特基势垒材料。 沟槽在N型半导体衬底中打开，并且掺杂区包括设置在沟槽下方的P掺杂区构成浮岛。 P掺杂的浮岛可以在沟槽底部形成为垂直阵列。

公开(公告)号：US20120161304A1

公开(公告)日：2012-06-28

申请号：US13411990

申请日：2012-03-05

申请人： Kai Liu ,  Lei Shi ,  Jun Lu ,  Anup Bhalla

发明人： Kai Liu ,  Lei Shi ,  Jun Lu ,  Anup Bhalla

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/24247 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92246 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路容量。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。

公开(公告)号：US20120104555A1

公开(公告)日：2012-05-03

申请号：US12925869

申请日：2010-10-31

申请人： Madhur Bobde ,  Anup Bhalla

发明人： Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66348

摘要： This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

摘要翻译： 本发明公开了一种形成在半导体衬底中的绝缘栅双极晶体管（IGBT）器件。 IGBT器件具有分裂屏蔽沟槽栅极，其包括上栅极段和下屏蔽段。 IGBT器件还可以包括填充有离开分屏蔽沟槽栅极一定距离设置的电介质层的虚拟沟槽。 IGBT器件还包括在分屏蔽沟槽栅极和虚拟沟槽之间延伸的体区，其围绕半导体衬底的顶表面附近的分离屏蔽沟槽栅极的源极区域。 所述IGBT器件还包括设置在所述体区域的下方且位于所述半导体衬底的底表面的底体 - 掺杂剂集电极区域上方的源 - 掺杂剂漂移区上方的重掺杂N区域。 在替代实施例中，IGBT可以包括具有沟槽屏蔽电极的平面栅极。

公开(公告)号：US08110869B2

公开(公告)日：2012-02-07

申请号：US11906476

申请日：2007-10-01

申请人： Anup Bhalla

发明人： Anup Bhalla

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

摘要翻译： 一种半导体功率器件，其被支撑在第一导电类型的半导体衬底上，底层用作底部电极，外延层覆盖在与底层相同的导电类型的底层上。 半导体功率器件包括多个FET单元，并且每个单元还包括从顶表面延伸到外延层中的第二导电类型的体区。 身体区域包括第二导电类型的重体掺杂区域。 绝缘栅极设置在外延层的顶表面上，与身体区域的第一部分重叠。 屏障控制层设置在远离绝缘栅极的身体区域旁边的外延层的顶表面上。 覆盖覆盖主体区域的第二部分的外延层的顶表面上的导电层和在形成肖特基结二极管的势垒控制层上延伸的重体掺杂区域。

公开(公告)号：US08105895B2

公开(公告)日：2012-01-31

申请号：US12932163

申请日：2011-02-17

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US08093651B2

公开(公告)日：2012-01-10

申请号：US12005146

申请日：2007-12-21

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66484 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and at least part of the body into the drain, wherein the active region contact trench is shallower than the body bottom surface, and an active region contact electrode disposed within the active region contact trench.

摘要翻译： 半导体器件形成在半导体衬底上。 该器件包括漏极，覆盖漏极的外延层和有源区。 有源区域包括设置在外延层中的主体，具有主体顶表面和主体底表面，嵌入在主体中的源，从主体顶表面延伸到主体中，延伸到外延层中的栅沟槽， 设置在所述栅极沟槽中的栅极，延伸穿过所述源极和所述主体的至少一部分进入所述漏极的有源区接触沟槽，其中所述有源区接触沟槽比所述主体底表面浅，以及设置在所述栅极沟槽内的有源区接触电极 有源区接触沟槽。

公开(公告)号：US20110233666A1

公开(公告)日：2011-09-29

申请号：US12731112

申请日：2010-03-24

申请人： Sik Lui ,  Anup Bhalla

发明人： Sik Lui ,  Anup Bhalla

IPC分类号： H01L27/105 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/32133 ,  H01L21/76224 ,  H01L27/088 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7827

摘要： An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process.

摘要翻译： 氧化物终端半导体器件可以包括多个栅极沟槽，栅极流道和绝缘体端接沟槽。 栅极沟槽位于有源区域中。 每个栅极沟槽包括导电栅电极。 绝缘体端接沟槽位于围绕有源区域的端接区域中。 绝缘体端接沟槽填充有绝缘体材料以形成用于半导体器件的绝缘子端子。 该装置可以使用三掩模或四掩模工艺制成。

公开(公告)号：US20110204440A1

公开(公告)日：2011-08-25

申请号：US13066947

申请日：2011-04-28

申请人： Anup Bhalla ,  Sik K. Lui

发明人： Anup Bhalla ,  Sik K. Lui

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device that includes a plurality of power transistor cells surrounded by a trench opened in a semiconductor substrate. At least one of the cells constituting an active cell has a source region disposed next to a trenched gate electrically connecting to a gate pad and surrounding the cell. The trenched gate further has a bottom-shielding electrode filled with a gate material disposed below and insulated from the trenched gate. At least one of the cells constituting a source-contacting cell surrounded by the trench with a portion functioning as a source connecting trench is filled with the gate material for electrically connecting between the bottom-shielding electrode and a source metal disposed directly on top of the source connecting trench. The semiconductor power device further includes an insulation protective layer disposed on top of the semiconductor power device having a plurality of source openings on top of the source region and the source connecting trench provided for electrically connecting to the source metal and at least a gate opening provided for electrically connecting the gate pad to the trenched gate.

摘要翻译： 本发明公开了一种半导体功率器件，其包括由在半导体衬底中开口的沟槽围绕的多个功率晶体管单元。 构成活性单元的单元中的至少一个具有与沟槽栅极相邻设置的源极区域，该沟槽栅极电连接到栅极焊盘并围绕电池。 沟槽栅极还具有填充有栅极材料的底部屏蔽电极，栅极材料设置在沟槽栅极下方并与沟槽栅极绝缘。 构成由沟槽围绕的源极接触单元中的至少一个具有用作源极连接沟槽的部分的单元填充有栅极材料，用于电连接底部屏蔽电极和直接设置在源极连接沟槽顶部的源极金属 源连接沟槽。 半导体功率器件还包括设置在半导体功率器件的顶部上的绝缘保护层，其具有在源极区域的顶部上的多个源极开口和设置用于电连接到源极金属的源极连接沟槽和至少提供的栅极开口 用于将栅极焊盘电连接到沟槽栅极。

公开(公告)号：US07952144B2

公开(公告)日：2011-05-31

申请号：US12860777

申请日：2010-08-20

申请人： Yi Su ,  Anup Bhalla ,  Daniel Ng

发明人： Yi Su ,  Anup Bhalla ,  Daniel Ng

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7815 ,  H01L2224/0603 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common substrate. The main FET and each of the sense FETs include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and the one or more sense FETs. An electrical isolation is disposed between the gate terminals of the main FET and the one or more sense FETs. Embodiments of this invention may be applied to both N-channel and P-channel MOSFET devices.

摘要翻译： 半导体器件包括主场效应晶体管（FET）和一个或多个感测FET以及公共栅极焊盘。 主FET和一个或多个感测FET形成在公共衬底中。 主FET和每个感测FET包括源极端子，栅极端子和漏极端子。 公共栅极焊盘连接主FET和一个或多个感测FET的栅极端子。 在主FET和一个或多个感测FET的栅极端子之间设置电隔离。 本发明的实施例可以应用于N沟道和P沟道MOSFET器件。

公开(公告)号：US20110103148A1

公开(公告)日：2011-05-05

申请号：US12589945

申请日：2009-10-30

申请人： Anup Bhalla ,  Tinggang Zhu

发明人： Anup Bhalla ,  Tinggang Zhu

IPC分类号： G11C16/04 ,  H01L31/00 ,  H01L21/337

CPC分类号： H01L29/7787 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/785

摘要： A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer. The power device further includes a floating gate located between the gate electrode and hetero-junction structure, wherein the gate electrode is insulated from the floating gate with an insulation layer and wherein the floating gate is disposed above and padded with a thin insulation layer from the hetero-junction structure and wherein the floating gate is charged for continuously applying a voltage to the 2DEG layer to pinch off the current flowing in the 2DEG layer between the source and drain electrodes whereby the HFET semiconductor power device is a normally off device.

摘要翻译： 异质结场效应晶体管（HFET）氮化镓（GaN）半导体功率器件包括异质结结构，其包括与两个不同带隙的第二半导体层接口的第一半导体层，从而产生作为二维电子气的界面层 2DEG）层。 功率器件还包括设置在异质结结构的顶部上的栅电极的两个相对侧上的源电极和漏电极，用于控制2DEG层中的源电极和漏电极之间的电流。 功率器件还包括位于栅电极和异质结结构之间的浮动栅极，其中栅电极与浮栅绝缘，并具有绝缘层，并且其中浮置栅极位于上方并且填充有薄绝缘层 异质结结构，并且其中浮置栅极被充电以连续地向2DEG层施加电压以夹紧在源极和漏极之间的2DEG层中流动的电流，由此HFET半导体功率器件是常闭装置。