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公开(公告)号：US20120161304A1
公开(公告)日：2012-06-28
申请号：US13411990
申请日：2012-03-05
申请人： Kai Liu , Lei Shi , Jun Lu , Anup Bhalla
发明人： Kai Liu , Lei Shi , Jun Lu , Anup Bhalla
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49589 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L2224/24247 , H01L2224/291 , H01L2224/2919 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/92246 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.
摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路容量。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。
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公开(公告)号：US08709867B2
公开(公告)日：2014-04-29
申请号：US13411990
申请日：2012-03-05
申请人： Kai Liu , Lei Shi , Jun Lu , Anup Bhalla
发明人： Kai Liu , Lei Shi , Jun Lu , Anup Bhalla
IPC分类号： H01L21/00
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49589 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L2224/24247 , H01L2224/291 , H01L2224/2919 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/92246 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.
摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路容量。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。
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公开(公告)号：US08154108B2
公开(公告)日：2012-04-10
申请号：US12749505
申请日：2010-03-29
申请人： Kai Liu , Lei Shi , Jun Lu , Anup Bhalla
发明人： Kai Liu , Lei Shi , Jun Lu , Anup Bhalla
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49589 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L2224/24247 , H01L2224/291 , H01L2224/2919 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/92246 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacitor configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.
摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路电容器。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。
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公开(公告)号：US20110233746A1
公开(公告)日：2011-09-29
申请号：US12749505
申请日：2010-03-29
申请人： Kai Liu , Lei Shi , Jun Lu , Anup Bhalla
发明人： Kai Liu , Lei Shi , Jun Lu , Anup Bhalla
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49589 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/92 , H01L2224/24247 , H01L2224/291 , H01L2224/2919 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/92246 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.
摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路容量。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。
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公开(公告)号：US08581376B2
公开(公告)日：2013-11-12
申请号：US12819111
申请日：2010-06-18
申请人： Hamza Yilmaz , Xiaotian Zhang , Yan Xun Xue , Anup Bhalla , Jun Lu , Kai Liu , Yueh-Se Ho , John Amato
发明人： Hamza Yilmaz , Xiaotian Zhang , Yan Xun Xue , Anup Bhalla , Jun Lu , Kai Liu , Yueh-Se Ho , John Amato
CPC分类号： H01L23/49541 , H01L23/3107 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/81 , H01L24/84 , H01L2224/27013 , H01L2224/29101 , H01L2224/2929 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/48247 , H01L2224/84801 , H01L2224/8485 , H01L2224/92 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01067 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2224/81 , H01L2224/84 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.
摘要翻译： 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。
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公开(公告)号：US20110227207A1
公开(公告)日：2011-09-22
申请号：US12819111
申请日：2010-06-18
申请人： Hamza Yilmaz , Xiaotian Zhang , Yan Xun Xue , Anup Bhalla , Jun Lu , Kai Liu , Yueh-Se Ho , John Amato
发明人： Hamza Yilmaz , Xiaotian Zhang , Yan Xun Xue , Anup Bhalla , Jun Lu , Kai Liu , Yueh-Se Ho , John Amato
IPC分类号： H01L23/52 , H01L23/495 , H01L21/00
CPC分类号： H01L23/49541 , H01L23/3107 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/81 , H01L24/84 , H01L2224/27013 , H01L2224/29101 , H01L2224/2929 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45014 , H01L2224/48247 , H01L2224/84801 , H01L2224/8485 , H01L2224/92 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01067 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2224/81 , H01L2224/84 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.
摘要翻译： 本发明涉及具有插入金属夹结构的半导体管芯堆叠的引线框架。 水平投影从夹子结构延伸，以确保夹子结构在制造过程中保持水平。
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公开(公告)号：US08513784B2
公开(公告)日：2013-08-20
申请号：US12726892
申请日：2010-03-18
申请人： Jun Lu , Ming Sun , Yueh-Se Ho , Kai Liu , Lei Shi
发明人： Jun Lu , Ming Sun , Yueh-Se Ho , Kai Liu , Lei Shi
IPC分类号： H01L23/495 , H01L23/48
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/37 , H01L24/38 , H01L24/40 , H01L24/41 , H01L24/83 , H01L24/84 , H01L24/97 , H01L2224/2919 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40249 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/73263 , H01L2224/83 , H01L2224/83801 , H01L2224/8385 , H01L2224/8485 , H01L2224/92 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2224/84 , H01L2924/0665 , H01L2924/00 , H01L2924/00015 , H01L2924/00012 , H01L2924/00014
摘要： The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.
摘要翻译： 本发明的特征在于具有第一，第二，第三和第四导电结构的引线框架封装，其中设置在其间的一对半导体管芯限定堆叠结构。 第一和第二结构与第一结构隔开并与第一结构重叠。 半导体管芯设置在第一和第二结构之间。 半导体管芯具有电连接到第一和第二结构的触点。 第三结构的一部分位于具有第二结构的一部分的共同平面中。 第三结构耦合到半导体管芯。 附加的半导体管芯附接到第一和第二结构中的一个。 第四结构与附加的半导体管芯电接触。 设置模塑料以封装所述包装的一部分，其中模制化合物的一部分设置在体积中。
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公开(公告)号：US20110227205A1
公开(公告)日：2011-09-22
申请号：US12726892
申请日：2010-03-18
申请人： Jun Lu , Ming Sun , Yueh-Se Ho , Kai Liu , Lei Shi
发明人： Jun Lu , Ming Sun , Yueh-Se Ho , Kai Liu , Lei Shi
IPC分类号： H01L23/52 , H01L21/60 , H01L23/538
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/37 , H01L24/38 , H01L24/40 , H01L24/41 , H01L24/83 , H01L24/84 , H01L24/97 , H01L2224/2919 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40249 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/73263 , H01L2224/83 , H01L2224/83801 , H01L2224/8385 , H01L2224/8485 , H01L2224/92 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2224/84 , H01L2924/0665 , H01L2924/00 , H01L2924/00015 , H01L2924/00012 , H01L2924/00014
摘要： The present invention features a lead-frame package, having a first, second, third and fourth electrically conductive structures with a pair of semiconductor dies disposed therebetween defining a stacked structure. The first and second structures are spaced-apart from and in superimposition with the first structure. A semiconductor die is disposed between the first and second structures. The semiconductor die has contacts electrically connected to the first and second structures. A part of the third structure lies in a common plane with a portion of the second structure. The third structure is coupled to the semiconductor die. An additional semiconductor die is attached to one of the first and second structures. The fourth structure is in electrical contact with the additional semiconductor die. A molding compound is disposed to encapsulate a portion of said package with a sub-portion of the molding compound being disposed in the volume.
摘要翻译： 本发明的特征在于具有第一，第二，第三和第四导电结构的引线框架封装，其中设置在其间的一对半导体管芯限定堆叠结构。 第一和第二结构与第一结构隔开并与第一结构重叠。 半导体管芯设置在第一和第二结构之间。 半导体管芯具有电连接到第一和第二结构的触点。 第三结构的一部分位于具有第二结构的一部分的共同平面中。 第三结构耦合到半导体管芯。 附加的半导体管芯附接到第一和第二结构中的一个。 第四结构与附加的半导体管芯电接触。 设置模塑料以封装所述包装的一部分，其中模制化合物的一部分设置在体积中。
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公开(公告)号：US08247288B2
公开(公告)日：2012-08-21
申请号：US12947717
申请日：2010-11-16
申请人： Yan Xun Xue , Anup Bhalla , Hamza Yilmaz , Jun Lu
发明人： Yan Xun Xue , Anup Bhalla , Hamza Yilmaz , Jun Lu
IPC分类号： H01L21/8242
CPC分类号： H01L23/5223 , H01L23/49562 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/0629 , H01L27/0688 , H01L28/88 , H01L2224/04042 , H01L2224/05001 , H01L2224/0554 , H01L2224/05552 , H01L2224/05554 , H01L2224/0603 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49111 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/10253 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19107 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/85399 , H01L2224/05599
摘要： A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.
摘要翻译： 旁路电容直接集成在MOSFET芯片的顶部。 电容器包括多层导电材料和电介质材料，它们通过介电层连接不同导电层的连接通孔彼此顶部。 集成旁路电容器的方法包括沉积介电层的重复步骤，形成通过电介质层的连接通孔，沉积导电层和图案化导电层。
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公开(公告)号：US20120025360A1
公开(公告)日：2012-02-02
申请号：US12846034
申请日：2010-07-29
申请人： Yan Xun Xue , Anup Bhalla , Jun Lu
发明人： Yan Xun Xue , Anup Bhalla , Jun Lu
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2224/29139 , H01L2224/32245 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40248 , H01L2224/40249 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73215 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/8385 , H01L2224/8485 , H01L2224/92246 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.
摘要翻译： 半导体封装包括引线框架，还包括芯片载体和与芯片载体相邻的多个引脚。 从芯片载体的上表面开放的多个槽将芯片载体部分地分成多个芯片安装区域。 去除凹槽的底部以完全隔离每个芯片安装区域，其中移除的凹槽的底部的宽度小于凹槽的宽度。 在一个实施例中，凹槽位于芯片载体和引脚之间，其中凹槽的底部被移除以将引脚与芯片载体隔离开，其中移除的凹槽的底部的宽度小于凹槽的宽度 。
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