公开(公告)号：US08673728B2

公开(公告)日：2014-03-18

申请号：US13667657

申请日：2012-11-02

Applicant: GlobalFoundries Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

IPC: H01L21/20

CPC classification number: H01L28/20 ,  H01L29/78 ,  H01L29/7843

Abstract: Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.

Abstract translation: 通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。 实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。 实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调谐电阻器的电阻。 使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。

公开(公告)号：US20130240988A1

公开(公告)日：2013-09-19

申请号：US13886373

申请日：2013-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Griebenow ,  Jan Hoentschel ,  Thilo Scheiper ,  Sven Beyer

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/84 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract translation: 在复杂的半导体器件中，替代栅极方法可以与用于实现应变诱导半导体材料的工艺策略结合使用，其中应变诱导半导体材料的优越接近和/或替代栅极方法的优异鲁棒性可以通过 形成具有优异均匀性的初始栅电极结构，并且在非常先进的制造阶段，即在完成基本晶体管配置之后，提供用于实现应变通道区域的至少一个空腔。

公开(公告)号：US20130187209A1

公开(公告)日：2013-07-25

申请号：US13785480

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One semiconductor device includes a semiconductor substrate, a gate structure overlying the semiconductor substrate, stressor regions formed in the semiconductor substrate proximate the gate structure, and a silicon material overlying the stressor regions, the silicon material encapsulating the stressor regions.

Abstract translation: 提供了具有硅封装应力区域的半导体器件结构的装置和相关的制造方法。 一个半导体器件包括半导体衬底，覆盖半导体衬底的栅极结构，在栅极结构附近形成在半导体衬底中的应力区域以及覆盖在应力区域上的硅材料，所述硅材料封装应力区域。

公开(公告)号：US20180012877A1

公开(公告)日：2018-01-11

申请号：US15713064

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/83 ,  H01L25/043 ,  H01L2224/16146 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044

Abstract: A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.

公开(公告)号：US09806067B2

公开(公告)日：2017-10-31

申请号：US14803466

申请日：2015-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/167 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/83 ,  H01L25/043 ,  H01L2224/16146 ,  H01L2224/818 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044

Abstract: A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to receive an optical signal from another die. Furthermore, a method of forming a semiconductor device is provided including forming a first semiconductor die with the steps of providing a semiconductor substrate, forming a transistor device at least partially over the semiconductor substrate, forming an optical receiver one of at least partially over and at least partially in the semiconductor substrate, forming a metallization layer over the transistor device, and forming an optical transmitter one of at least partially over the metallization layer and at least partially in the metallization layer.

公开(公告)号：US09698179B2

公开(公告)日：2017-07-04

申请号：US15042547

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Jan Hoentschel ,  Alexander Ebermann

IPC: H01L27/13 ,  H01L49/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/13 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1207 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/78

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

公开(公告)号：US20170040450A1

公开(公告)日：2017-02-09

申请号：US14816337

申请日：2015-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sven Beyer ,  Tom Hasche ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L21/743 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/7838 ,  H01L29/7843

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

Abstract translation: 本公开根据一些说明性实施例提供了一种形成半导体器件的方法，所述方法包括提供SOI衬底，所述SOI衬底具有设置在掩埋绝缘材料层上的有源半导体层，所述有源半导体层又形成在基底衬底材料 在所述SOI衬底的有源区中的所述有源半导体层上形成栅极结构，在所述栅极结构形成之后，部分地露出所述基底以形成至少一个本体暴露区域，以及形成用于使所述至少一个 体积暴露区域。

公开(公告)号：US20160358915A1

公开(公告)日：2016-12-08

申请号：US15238023

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L27/11 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/28291 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.

Abstract translation: 半导体器件包括位于半导体衬底之上的半导体衬底和鳍，其中鳍包括半导体材料。 此外，铁电高k隔板覆盖翅片的侧壁表面，并且非铁电高k材料层覆盖铁电高k隔板和翅片，其中非铁电高k材料层的一部分被定位 在鳍的上表面上与半导体材料直接接触。

公开(公告)号：US20160300928A1

公开(公告)日：2016-10-13

申请号：US14684559

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Peter Javorka ,  Ralf Richter

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6653

Abstract: A method of manufacturing a semiconductor device is provided including forming replacement gates over a semiconductor layer, forming sidewall spacers at sidewalls of the replacement gates, forming a dielectric layer in interspaces between the sidewall spacers of neighboring replacement gates, removing the replacement gates and sidewall spacers to form openings in the dielectric layer, and forming gate electrodes in the openings.

Abstract translation: 提供了一种制造半导体器件的方法，包括在半导体层上形成替代栅极，在替换栅极的侧壁处形成侧壁间隔物，在相邻替代栅极的侧壁间隔件之间的间隙中形成介电层，去除替换栅极和侧壁间隔物 以在电介质层中形成开口，并在开口中形成栅电极。

公开(公告)号：US09443945B2

公开(公告)日：2016-09-13

申请号：US14600097

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L27/01 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.