公开(公告)号：US20160049490A1

公开(公告)日：2016-02-18

申请号：US14924151

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy Wei

IPC: H01L29/45 ,  H01L27/092

CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41725

Abstract: Integrated circuits with dual silicide contacts are provided. In an embodiment, an integrated circuit includes a semiconductor substrate including a first area and a second area. The integrated circuit includes a first source/drain region in and/or overlying the first area of the semiconductor substrate and a second source/drain region in and/or overlying the second area of the semiconductor substrate. The integrated circuit further includes a first contact over the first source/drain region and comprising a first metal silicide. The integrated circuit also includes a second contact over the second source/drain region and comprising a second metal silicide different from the first metal silicide.

Abstract translation: 提供了具有双硅化物触点的集成电路。 在一个实施例中，集成电路包括包括第一区域和第二区域的半导体衬底。 集成电路包括位于半导体衬底的第一区域内和/或覆盖半导体衬底的第一区域的第一源极/漏极区域和位于半导体衬底的第二区域内和/或覆盖半导体衬底的第二区域中的第二源极/漏极区域。 集成电路还包括在第一源极/漏极区域上的第一接触并且包括第一金属硅化物。 集成电路还包括在第二源极/漏极区域上的第二接触并且包括不同于第一金属硅化物的第二金属硅化物。

公开(公告)号：US09177951B2

公开(公告)日：2015-11-03

申请号：US14148221

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

Abstract translation: 三维静电放电（ESD）半导体器件与三维非ESD半导体器件一起制造。 例如，ESD二极管和FinFET制造在相同的体半导体衬底上。 衬底合并技术用于衬底的ESD部分中以形成双宽度鳍片，其上可以使ESD器件更大以处理更多的电流。

公开(公告)号：US20150228755A1

公开(公告)日：2015-08-13

申请号：US14177800

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Andy Wei ,  Jin Ping Liu ,  Shao Ming Koh ,  Amaury Gendron

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/6681 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.

Abstract translation: 提供了具有松散硅和锗翅片的集成电路以及用于制造这种集成电路的方法。 该方法包括形成覆盖晶体硅衬底的晶体硅和锗复合层，其中复合层晶格被放宽。 在复合层中形成翅片，并且在翅片上形成栅极。 翅片的一部分在栅极的相对侧上被去除以形成漏腔和源腔，并且源极和漏极分别形成在源极腔和漏极腔中。

公开(公告)号：US09105478B2

公开(公告)日：2015-08-11

申请号：US14064840

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Wei ,  Mariappan Hariharaputhiran ,  Dae Geun Yang ,  Dae-Han Choi ,  Xiang Hu ,  Richard J. Carter ,  Akshey Sehgal

IPC: H01L21/302 ,  H01L21/033 ,  G03F1/50

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

公开(公告)号：US20150123211A1

公开(公告)日：2015-05-07

申请号：US14070607

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qi Zhang ,  Hongliang Shen ,  Zhenyu Hu ,  Andy Wei ,  Zhuangfei Chen ,  Nicholas V. LiCausi

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/324 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211

Abstract: Approaches for providing a narrow diffusion break in a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device is provided with a set of fins formed from a substrate, and an opening formed through the set of fins, the opening oriented substantially perpendicular to an orientation of the set of fins. This provides a FinFET device capable of achieving cross-the-fins insulation with an opening size that is adjustable from approximately 20-30 nm.

Abstract translation: 公开了在鳍式场效应晶体管（FinFET）器件中提供窄扩散断裂的方法。 具体地，FinFET器件设置有由基板形成的一组翅片，以及通过该组翅片形成的开口，该开口基本上垂直于该组翅片的取向定向。 这提供了一种FinFET器件，其能够实现跨鳍片绝缘，其开口尺寸可从大约20-30nm调节。

公开(公告)号：US08742510B2

公开(公告)日：2014-06-03

申请号：US13718158

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Andy Wei ,  Richard Carter

IPC: H01L21/70 ,  H01L21/02 ,  H01L23/48 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures. Furthermore, the device also includes, among other things, a conductive contact positioned between the plurality of gate structures, the conductive contact having a lower portion that conductively contacts the metal silicide region and an upper portion positioned above the lower portion, wherein the lower portion is laterally wider than the upper portion and extends laterally so as to contact the sidewall spacers positioned proximate each of the gate structures.

Abstract translation: 这里公开了在半导体器件上形成替代栅极结构和导电触点的各种方法以及包括该栅极结构和导电触点的装置。 一个示例性器件包括位于半导体衬底上方的多个栅极结构，位于栅极结构的相应侧壁附近的至少一个侧壁隔离物，以及在半导体衬底的源极/漏极区域中的金属硅化物区域，金属硅化物区域延伸 横向地接触定位在每个栅极结构附近的侧壁间隔件。 此外，该装置还包括位于多个栅极结构之间的导电触点，导电触点具有导电接触金属硅化物区域的下部分和位于下部部分上方的上部，其中下部分 横向宽于上部并且横向延伸，以便接近靠近每个门结构的侧壁间隔件。

公开(公告)号：US20140134822A1

公开(公告)日：2014-05-15

申请号：US13678011

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Gopal Srinivasan ,  Andy Wei ,  Dinesh Somasekhar ,  Ali Keshavarzi ,  Subi Kengeri

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78648

Abstract: A method for fabricating a FinFET integrated circuit includes depositing a first polysilicon layer at a first end of a diffusion region and a second polysilicon layer at a second end of the diffusion region; diffusing an n-type material into the diffusion region to form a diffused resistor; and epitaxially growing a silicon material between the first and second polysilicon layers to form fins structures over the diffused resistor and spanning between the first and second polysilicon layers.

Abstract translation: 一种制造FinFET集成电路的方法包括在扩散区的第二端处沉积第一多晶硅层，在扩散区的第二端沉积第二多晶硅层; 将n型材料扩散到扩散区域中以形成扩散电阻器; 并且在所述第一和第二多晶硅层之间外延生长硅材料，以在所述扩散电阻器上方形成翅片结构并跨越所述第一和第二多晶硅层。