公开(公告)号：US09679985B1

公开(公告)日：2017-06-13

申请号：US15187080

申请日：2016-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Haigou Huang

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L29/42356 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66795

Abstract: Devices and methods of fabricating integrated circuit devices for increasing performance through gate cut last processes are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a plurality of fins, an STI layer, an oxide layer, and a gate material over the oxide layer, the fins extending into the gate material; removing the gate material and the oxide layer; depositing a high k material on a top surface of the STI layer, surrounding the fins; depositing a gate stack over the high k material; filling the top of the device with a gate contact metal; etching a portion of the gate contact metal, the metal gate stack, and the high k material; and filling the portion with an inter-layer dielectric. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US09601392B1

公开(公告)日：2017-03-21

申请号：US14927943

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ming Lei ,  Byoung-Gi Min ,  Xusheng Wu

IPC: H01L21/66 ,  H01L27/11

CPC classification number: H01L22/14 ,  G11C11/4125 ,  G11C29/50008 ,  G11C2029/5002 ,  H01L22/30 ,  H01L22/34 ,  H01L27/1104

Abstract: A method and device for characterizing a DC parameter of a SRAM device based on TDCD are provided. Embodiments include forming a SRAM test device, the SRAM test device having a top edge and a bottom edge and at least a first and a second S/D contact, a gate contact, and a channel region; inducing an inversion charge in the channel region through the gate contact; scanning the first S/D contact with an ebeam subsequent to inducing the inversion charge; and characterizing at least one DC parameter of the SRAM test device based on a dissipation of the inversion charge between the steps of inducing and scanning

公开(公告)号：US09564375B2

公开(公告)日：2017-02-07

申请号：US14054040

申请日：2013-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy Mann ,  Sandeep Puri ,  Sonia Ghosh ,  Anuj Gupta ,  Xusheng Wu

IPC: G06F17/50 ,  H01L21/66

CPC classification number: H01L22/14 ,  G01B2210/56 ,  G06F17/5063 ,  G06F17/5068

Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.

Abstract translation: 公开了用于提取晶体管沟道宽度的方法和设计结构。 实施例可以包括根据晶体管的拉出沟道宽度确定多个集成电路的晶体管的有效沟道宽度，以及基于有效沟道宽度确定目标晶体管的目标沟道宽度。

公开(公告)号：US09543297B1

公开(公告)日：2017-01-10

申请号：US14869397

申请日：2015-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Konstantin G. Korablev ,  Shesh Mani Pandey ,  Manfred Eller

IPC: H01L21/82 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/66795

Abstract: A method of forming fins and the resulting fin-shaped field effect transistors (finFET) are provided. Embodiments include forming silicon (Si) fins over a substrate; forming a first metal over each of the Si fins; forming an isolation material over the first metal; removing an upper portion of the isolation material to expose and upper portion of the first metal; removing the upper portion of the first metal to expose an upper portion of each Si fin; removing the isolation material after removing the upper portion of the first metal; and forming a second metal over the first metal and the upper portion of the Si fins.

Abstract translation: 提供了一种形成翅片的方法和所得的鳍状场效应晶体管（finFET）。 实施例包括在衬底上形成硅（Si）鳍; 在每个Si散热片上形成第一金属; 在所述第一金属上形成隔离材料; 去除所述隔离材料的上部以暴露所述第一金属的上部; 去除第一金属的上部以暴露每个Si散热片的上部; 在去除第一金属的上部之后去除隔离材料; 以及在所述第一金属和所述Si翅片的上部上形成第二金属。

公开(公告)号：US20160358851A1

公开(公告)日：2016-12-08

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US09418899B1

公开(公告)日：2016-08-16

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping Shen ,  Min-hwa Chi ,  Xusheng Wu ,  Weihua Tong ,  Haiting Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/3215 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直放置第二Ti层中的Al或C; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。

公开(公告)号：US09337306B2

公开(公告)日：2016-05-10

申请号：US14319462

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Xusheng Wu ,  Hong Yu ,  Zhao Lun

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/6656 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.

Abstract translation: 提供了用于形成外延（epi）源极/漏极（S / D）和/或具有外延S / D的半导体器件的方法。 在本发明的实施例中，epi S / D的第一部分形成在鳍状衬底中的翅片上的S / D区域中。 在形成第一部分之后，但在形成S / D之前，在S / D区域中形成二次间隔物。 然后，在S / D区域中形成S / D的剩余部分。 结果，S / D通过辅助间隔件与栅极堆叠分离。

公开(公告)号：US09087720B1

公开(公告)日：2015-07-21

申请号：US14450535

申请日：2014-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Manfred Eller ,  Wanxun He ,  Jie Chen

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/26513 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming FinFETs with reduced series resistance includes providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate, a gate disposed over a first portion of the fin, and a first sidewall spacer disposed over the fin and adjacent to the gate, increasing epitaxially the thickness of a second portion of the fin disposed outside the gate and the first sidewall spacer, and forming a second sidewall spacer disposed over the second portion of the fin and adjacent to the first sidewall spacer. A thickness of the second portion of the fin disposed under the second spacer is equal to or greater than a thickness of the first portion of the fin disposed under the gate.

Abstract translation: 用于形成具有降低的串联电阻的FinFET的方法包括提供包括半导体衬底的中间半导体结构，设置在半导体衬底上的鳍，设置在鳍的第一部分上的栅极和设置在鳍上并邻近 到外部延伸设置在栅极和第一侧壁间隔物外部的翅片的第二部分的厚度，以及形成设置在翅片的第二部分上并邻近第一侧壁间隔物的第二侧壁间隔物。 设置在第二间隔件下方的翅片的第二部分的厚度等于或大于设置在浇口下方的翅片的第一部分的厚度。

公开(公告)号：US20150091097A1

公开(公告)日：2015-04-02

申请号：US14043871

申请日：2013-10-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Bingwu Liu ,  Randy Mann

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L27/1104 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/66803 ,  H01L29/785

Abstract: Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

Abstract translation: 公开了用于提供在半导体器件的静态随机存取存储器（SRAM）布局的晕圈/扩展注入期间使用的硬掩模的方法。 具体地，提供了用于在衬底上形成下拉（PD）晶体管的方法; 在衬底上形成栅极（PG）晶体管; 以及在所述器件上构图硬掩模，所述硬掩模包括与所述PD晶体管相邻的第一部分和与所述PG晶体管相邻的第二部分，其中所述第一部分与所述PD晶体管之间的距离小于所述第二部分与所述PG之间的距离 晶体管。 选择第一部分和PD晶体管以及第二部分和PG晶体管之间的相应距离以防止光晕/延伸注入物撞击PD晶体管的一侧，同时允许光晕/延伸植入物撞击两侧 的PG晶体管。

公开(公告)号：US20140264613A1

公开(公告)日：2014-09-18

申请号：US13835944

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xiaodong Yang ,  Jin Ping Liu ,  Yanxiang Liu ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，半导体衬底包括设置在其中的浅沟槽隔离结构。 栅电极结构覆盖半导体衬底的半导体材料。 形成与栅电极结构相邻的第一侧壁间隔物，其中浅沟槽隔离结构的第一表面暴露并与第一侧壁间隔物隔开半导体材料的区域。 浅沟槽隔离结构的第一表面用隔离结构掩模掩蔽。 半导体材料的区域没有隔离结构掩模。 在半导体材料的区域中蚀刻凹陷，隔离结构掩模就位。 半导体材料在凹槽内外延生长以形成与栅电极结构相邻的外延生长的半导体区域。