公开(公告)号：US20210351283A1

公开(公告)日：2021-11-11

申请号：US16866663

申请日：2020-05-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Elizabeth A. Strehlow ,  Harold Mendoza ,  Jay A. Mody ,  Clynn J. Mathew ,  Hong Yu ,  Yea-Sen Lin

IPC: H01L29/66 ,  H01L29/10 ,  H01L27/06 ,  H01L27/088

Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

公开(公告)号：US11004953B2

公开(公告)日：2021-05-11

申请号：US16454016

申请日：2019-06-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Rinus Tek Po Lee ,  Hui Zang ,  Jiehui Shu ,  Hong Yu ,  Wei Hong

IPC: H01L29/66 ,  H01L21/8234

Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening. A second material layer is formed over the first material layer on the exposed upper portions of the first material layer in the second opening. An intermix layer is formed in the second opening using the first and second material layers. The protective layer from the second opening is removed to expose the first material layer.

公开(公告)号：US20250029869A1

公开(公告)日：2025-01-23

申请号：US18353995

申请日：2023-07-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu

IPC: H01L21/762 ,  H01L21/768

Abstract: An isolation structure for a substrate is disclosed. The isolation structure includes a lower portion having a first liner, and an upper portion having a second liner vertically over the first liner. A first dielectric material is surrounded by the second liner from above and by the first liner from below and laterally. The second liner may include a second dielectric material in at least part thereof. The second liner prevents exposure of end surfaces of a semiconductor layer of the substrate during subsequent processing, which prevents damage such as thinning, agglomeration and/or oxidation that can negatively affect performance of a transistor formed using the semiconductor layer. The second liner also reduces an overall step height of the isolation structure.

公开(公告)号：US12205949B1

公开(公告)日：2025-01-21

申请号：US18758069

申请日：2024-06-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhenyu Hu ,  Hong Yu ,  Haiting Wang

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.

公开(公告)号：US20240387668A1

公开(公告)日：2024-11-21

申请号：US18199054

申请日：2023-05-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  David C. Pritchard ,  Navneet K. Jain ,  James P. Mazza ,  Romain H. A. Feuillette

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

公开(公告)号：US20240347638A1

公开(公告)日：2024-10-17

申请号：US18301382

申请日：2023-04-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette ,  James P. Mazza ,  Hong Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28123 ,  H01L29/1037 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.

公开(公告)号：US20240274603A1

公开(公告)日：2024-08-15

申请号：US18169304

申请日：2023-02-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： David Charles Pritchard ,  James P. Mazza ,  Navneet K. Jain ,  Hong Yu

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/092 ,  H01L21/76224 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207

Abstract: A standard cell or integrated circuit (IC) structure includes a substrate including a first active region and a second active region. A first gate electrode is over the first active region; and a second gate electrode over the second active region. A trench isolation electrically isolates the first active region and the first gate electrode from the second active region and the second gate electrode. First ends of the first active region and the first gate electrode abut a first sidewall of the trench isolation and first ends of the second active region and the second gate electrode abut a second, opposing sidewall of the trench isolation. A conductive strap extends over an upper end of the trench isolation and electrically couples the first gate electrode and the second gate electrode.

公开(公告)号：US12020937B2

公开(公告)日：2024-06-25

申请号：US17701759

申请日：2022-03-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Man Gu ,  Eric S. Kozarsky

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3215 ,  H01L21/84 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L21/28052 ,  H01L21/28518 ,  H01L21/32155 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/45 ,  H01L29/4933

Abstract: Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.

公开(公告)号：US11908898B2

公开(公告)日：2024-02-20

申请号：US17456943

申请日：2021-11-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu ,  Alexander M. Derrickson

IPC: H01L29/10 ,  H01L29/735 ,  H01L29/66

CPC classification number: H01L29/1008 ,  H01L29/6625 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

公开(公告)号：US20240047555A1

公开(公告)日：2024-02-08

申请号：US17816799

申请日：2022-08-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anton V. Tokranov ,  Saloni Chaurasia ,  Hong Yu ,  Jagar Singh

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/66795 ,  H01L21/823431 ,  H01L21/823468

Abstract: A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.