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    Method of forming a metal layer
    52.
    发明申请
    Method of forming a metal layer 审中-公开
    形成金属层的方法

    公开(公告)号：US20050221000A1

    公开(公告)日：2005-10-06

    申请号：US10813680

    申请日：2004-03-31

    申请人： Taro Ikeda ,  Tsukasa Matsuda ,  Fenton McFeely ,  Sandra Malhotra ,  Andrew Simon ,  John Yurkas

    发明人： Taro Ikeda ,  Tsukasa Matsuda ,  Fenton McFeely ,  Sandra Malhotra ,  Andrew Simon ,  John Yurkas

    IPC分类号： C23C16/02 ,  C23C16/16 ,  C23C16/509 ,  B05D3/00 ,  C23C16/00 ,  H05H1/24

    CPC分类号： C23C16/5096 ,  C23C16/02 ,  C23C16/16

    摘要： A method and a processing tool are provided for forming a metal layer with improved morphology on a substrate. The method includes pre-treating the substrate by exposing the substrate to excited species in a plasma, exposing the pre-treated substrate to a process gas containing a metal-carbonyl precursor, and forming a metal layer on the pre-treated substrate surface by a chemical vapor deposition process. The metal-carbonyl precursor can contain W(CO)6, Ni(CO)4, Mo(CO)6, CO2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, or Ru3(CO)12 or any combination thereof, and the metal layer can contain W, Ni, Mo, Co, Rh, Re, Cr, or Ru, or any combination thereof, respectively.

    摘要翻译： 提供了一种用于在衬底上形成具有改善的形态的金属层的方法和加工工具。 该方法包括通过将衬底暴露于等离子体中的激发物质来预处理衬底，将预处理的衬底暴露于含有羰基金属前体的工艺气体中，以及在预处理的衬底表面上形成金属层 化学气相沉积工艺。 金属羰基前体可以含有W（CO）6，Ni（CO）4，Mo（CO）6，CO， 2（CO）8，Rh 4（CO）12，Re 2（CO） Cr（CO）6或Ru 3（CO）12 12或其任何组合，和 金属层可以分别含有W，Ni，Mo，Co，Rh，Re，Cr或Ru，或其任何组合。

    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate
    53.
    发明申请
    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 有权
    在半导体基板上筛选多个样品的组合处理方法

    公开(公告)号：US20110248264A1

    公开(公告)日：2011-10-13

    申请号：US12905945

    申请日：2010-10-15

    申请人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

    发明人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

    IPC分类号： H01L29/66

    CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

    摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

    Methods for treating substrates in preparation for subsequent processes
    54.
    发明授权
    Methods for treating substrates in preparation for subsequent processes 有权
    处理底物的方法用于后续方法的制备

    公开(公告)号：US07884036B1

    公开(公告)日：2011-02-08

    申请号：US11777152

    申请日：2007-07-12

    申请人： Jinhong Tong ,  Anh Duong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Sandra Malhotra ,  Tony Chiang

    发明人： Jinhong Tong ,  Anh Duong ,  Zhi-Wen Sun ,  Chi-I Lang ,  Sandra Malhotra ,  Tony Chiang

    IPC分类号： H01L21/00

    CPC分类号： H01L21/3105 ,  H01L21/02063 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76849

    摘要： Methods for treating a substrate in preparation for a subsequent process are presented, the method including: receiving the substrate, the substrate comprising conductive regions and dielectric regions; and applying an oxidizing agent to the substrate in a manner so that the dielectric regions are oxidized to become increasingly hydrophilic to enable access to the conductive regions in the subsequent process, wherein the dielectric region is treated to a depth in the range of approximately 1 to 5 atomic layers. In some embodiments, methods further include processing the substrate, wherein processing the conductive regions are selectively enhanced. In some embodiments, the oxidizing agent includes atmospheric pressure plasma and UV radiation.

    摘要翻译： 呈现用于处理衬底以用于后续工艺的方法，所述方法包括：接收衬底，所述衬底包括导电区域和电介质区域; 以及以使得电介质区域被氧化以变得越来越亲水的方式将氧化剂施加到衬底上，以便能够在随后的工艺中进入导电区域，其中将电介质区域处理到大约1至 5个原子层。 在一些实施例中，方法还包括处理衬底，其中选择性地增强对导电区域的处理。 在一些实施方案中，氧化剂包括大气压等离子体和UV辐射。

    Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
    56.
    发明申请
    Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region 有权
    在电介质区域上形成掩模层，以便在由电介质区域分隔的导电区域上形成覆盖层

    公开(公告)号：US20060264020A1

    公开(公告)日：2006-11-23

    申请号：US11132841

    申请日：2005-05-18

    申请人： David Lazovsky ,  Sandra Malhotra ,  Thomas Boussie

    发明人： David Lazovsky ,  Sandra Malhotra ,  Thomas Boussie

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76829 ,  B82Y30/00 ,  H01L21/02183 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76849

    摘要： A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

    摘要翻译： 在电子器件的电介质区域上形成掩模层，使得在随后在由电介质区域分离的电子器件的导电区域上形成覆盖层时，掩模层阻止在其上形成覆盖层材料 在电介质区域。 可以选择性地在导电区域或非选择性地形成覆盖层; 在任一情况下（特别是在后者中），可以随后去除在电介质区域上形成的覆盖层材料，从而确保覆盖层材料仅在导电区域上形成。 可以使用诸如硅烷基SAM之类的硅烷基材料来形成掩模层。 覆盖层可以由导电材料（例如，钴合金，镍合金，钨，钽，氮化钽），半导体材料或电绝缘材料形成，并且可以使用任何适当的工艺形成，包括 常规沉积工艺如无电沉积，化学气相沉积，物理气相沉积或原子层沉积。

    Constant emissivity deposition member
    58.
    发明申请
    Constant emissivity deposition member 失效
    恒辐射率沉积元件

    公开(公告)号：US20050260833A1

    公开(公告)日：2005-11-24

    申请号：US10851384

    申请日：2004-05-22

    申请人： Fenton McFeely ,  John Yurkas ,  Sandra Malhotra ,  Andrew Simon

    发明人： Fenton McFeely ,  John Yurkas ,  Sandra Malhotra ,  Andrew Simon

    IPC分类号： C23C16/44 ,  C30B1/00 ,  C30B35/00 ,  H01L21/20 ,  H01L21/285 ,  H01L21/36 ,  H01L21/44

    CPC分类号： C23C16/4404 ,  C30B35/00 ,  H01L21/28556

    摘要： A deposition member adapted for discharging a deposition material during a deposition process can acquire a coating during the deposition. Such an initial emissivity value is selected for the deposition member, before any of the coating became deposited, that the emissivity of the deposition member remains substantially unchanged during the deposition process. In a representative embodiment the deposition member is coated with an appropriate thin layer for achieving the selected emissivity value.

    摘要翻译： 适于在沉积过程中排出沉积材料的沉积构件可以在沉积期间获得涂层。 在任何涂层沉积之前，沉积构件选择这种初始发射率值，沉积构件的发射率在沉积过程中保持基本不变。 在代表性的实施例中，沉积构件涂覆有适当的薄层以实现所选择的发射率值。

    Low-pressure deposition of metal layers from metal-carbonyl precursors
    60.
    发明申请
    Low-pressure deposition of metal layers from metal-carbonyl precursors 有权
    金属 - 羰基前驱体金属层的低压沉积

    公开(公告)号：US20050070100A1

    公开(公告)日：2005-03-31

    申请号：US10673908

    申请日：2003-09-30

    申请人： Hideaki Yamasaki ,  Tsukasa Matsuda ,  Atsushi Gomi ,  Tatsuo Hatano ,  Masahito Sugiura ,  Yumiko Kawano ,  Gert Leusink ,  Fenton McFeely ,  Sandra Malhotra

    发明人： Hideaki Yamasaki ,  Tsukasa Matsuda ,  Atsushi Gomi ,  Tatsuo Hatano ,  Masahito Sugiura ,  Yumiko Kawano ,  Gert Leusink ,  Fenton McFeely ,  Sandra Malhotra

    IPC分类号： C23C16/16 ,  C23C16/44 ,  H01L21/285 ,  H01L21/44

    CPC分类号： C23C16/16 ,  H01L21/28556

    摘要： A method for depositing metal layers on semiconductor substrates by a thermal chemical vapor deposition (TCVD) process includes introducing a process gas containing a metal carbonyl precursor in a process chamber and depositing a metal layer on a substrate. The TCVD process utilizes a short residence time for the gaseous species in the processing zone above the substrate to form a low-resistivity metal layer. In one embodiment of the invention, the metal carbonyl precursor can be selected from at least one of W(CO)6, Ni(CO)4, Mo(CO)6, Co2(CO)8, Rh4(CO)12, Re2(CO)10, Cr(CO)6, and Ru3(CO)12 precursors. In another embodiment of the invention, a method is provided for depositing low-resistivity W layers at substrate temperatures below about 500° C., by utilizing a residence time less than about 120 msec.

    摘要翻译： 通过热化学气相沉积（TCVD）方法在金属层上沉积金属层的方法包括在处理室中引入含有羰基金属前驱体的工艺气体并在基底上沉积金属层。 TCVD工艺利用在衬底上方的处理区域中的气态物质的短暂停留时间以形成低电阻率金属层。 在本发明的一个实施方案中，金属羰基前体可以选自W（CO）6，Ni（CO）4，Mo（CO）6，Co 2（CO）8，Rh 4（CO）12，Re 2 （CO）10，Cr（CO）6和Ru 3（CO）12前体）。 在本发明的另一个实施例中，提供了一种通过利用小于约120毫秒的停留时间在低于约500℃的衬底温度下沉积低电阻W层的方法。