公开(公告)号：US20050158985A1

公开(公告)日：2005-07-21

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy Dalton ,  Kenneth Davis ,  Chao-Kun Hu ,  Fen Jamin ,  Steffen Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael Lofaro ,  Sandra Malhotra ,  Chandrasekhar Narayan ,  David Rath ,  Judith Rubino ,  Katherine Saenger ,  Andrew Simon ,  Sean Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy Dalton ,  Kenneth Davis ,  Chao-Kun Hu ,  Fen Jamin ,  Steffen Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael Lofaro ,  Sandra Malhotra ,  Chandrasekhar Narayan ,  David Rath ,  Judith Rubino ,  Katherine Saenger ,  Andrew Simon ,  Sean Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US20060258147A1

公开(公告)日：2006-11-16

申请号：US11405287

申请日：2006-04-17

申请人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

发明人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Anna Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

公开(公告)号：US20050062165A1

公开(公告)日：2005-03-24

申请号：US10666564

申请日：2003-09-19

申请人： Katherine Saenger ,  Maheswaran Surendra ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Matthew Colburn ,  Timothy Dalton ,  Elbert Huang

发明人： Katherine Saenger ,  Maheswaran Surendra ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Matthew Colburn ,  Timothy Dalton ,  Elbert Huang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

摘要翻译： 描述了形成闭合气隙互连结构的方法。 与存在于所述互连结构的其余部分的一个或多个牺牲介电质制成的互连线下永久支撑电介质的区域和周围的互连通孔的起始结构，覆盖有其使用模版具有规则穿孔的电介质阻挡 孔阵列 然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。 通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。 描述该方法的几个实施例和所得到的结构。

公开(公告)号：US20060267208A1

公开(公告)日：2006-11-30

申请号：US11405283

申请日：2006-04-17

申请人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

发明人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

摘要翻译： 描述了形成闭合气隙互连结构的方法。 在互连线下方由永久支撑电介质的区域构成的起始结构和在互连结构的其余部分中存在的具有一个或多个牺牲电介质的周围的互连通孔被封装有电介质阻挡层，其使用具有规则的模板 孔阵列 然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。 通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。 描述该方法的几个实施例和所得到的结构。

公开(公告)号：US20050037604A1

公开(公告)日：2005-02-17

申请号：US10949837

申请日：2004-09-24

申请人： Katherina Babich ,  Roy Carruthers ,  Timothy Dalton ,  Alfred Grill ,  Jeffrey Hedrick ,  Christopher Jahnes ,  Ebony Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Saenger

发明人： Katherina Babich ,  Roy Carruthers ,  Timothy Dalton ,  Alfred Grill ,  Jeffrey Hedrick ,  Christopher Jahnes ,  Ebony Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Saenger

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

摘要翻译： 描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。 还提供了形成这种互连结构的方法。 该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。

公开(公告)号：US20050196917A1

公开(公告)日：2005-09-08

申请号：US10790786

申请日：2004-03-03

申请人： Jingyu Lian ,  David Kotecki ,  Hua Shen ,  Robert Laibowitz ,  Katherine Saenger ,  Chenting Lin ,  Nicolas Nagel ,  Yunyu Wang ,  Satish Athavale ,  Thomas Shaw

发明人： Jingyu Lian ,  David Kotecki ,  Hua Shen ,  Robert Laibowitz ,  Katherine Saenger ,  Chenting Lin ,  Nicolas Nagel ,  Yunyu Wang ,  Satish Athavale ,  Thomas Shaw

IPC分类号： H01L21/8242

CPC分类号： H01L28/40 ,  H01L27/10852

摘要： A method for forming high capacitance crystalline dielectric layers with (111) texture is disclosed. In an exemplary embodiment, deposition of a plurality of nuclei is performed at a temperature in the range of about 430 to 460 degrees Celsius, followed by growth of a continuous BSTO dielectric layer at a temperature greater than 600 degrees Celsius. In an exemplary embodiment, a process is disclosed for growing a barium strontium titanium oxide film with high capacitance and thickness of about 30 nm or less.

摘要翻译： 公开了一种形成具有（111）结构的高电容结晶介电层的方法。 在一个示例性实施例中，多个核的沉积在约430至460摄氏度范围内的温度下进行，随后在大于600摄氏度的温度下生长连续的BSTO介电层。 在示例性实施例中，公开了用于生长具有约30nm或更小的高电容和厚度的钡锶氧化钛膜的方法。

公开(公告)号：US20070164337A1

公开(公告)日：2007-07-19

申请号：US11687000

申请日：2007-03-16

申请人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

发明人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  H01L27/0629 ,  H01L27/11502 ,  H01L27/11507 ,  Y10S438/977

摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

摘要翻译： 提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。 本发明的方法包括分别形成CMOS结构和铁电输送晶片。 然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。 然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。 电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。

公开(公告)号：US20060275971A1

公开(公告)日：2006-12-07

申请号：US11406122

申请日：2006-04-18

申请人： Keith Fogel ,  Kam-Leung Lee ,  Katherine Saenger ,  Chun-Yung Sung ,  Haizhou Yin

发明人： Keith Fogel ,  Kam-Leung Lee ,  Katherine Saenger ,  Chun-Yung Sung ,  Haizhou Yin

IPC分类号： H01L21/26

CPC分类号： H01L21/02675 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/76224 ,  H01L21/823807

摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

公开(公告)号：US20060244068A1

公开(公告)日：2006-11-02

申请号：US11116053

申请日：2005-04-27

申请人： Joel Desouza ,  Devendra Sadana ,  Katherine Saenger ,  Chun-yung Sung ,  Min Yang ,  Haizhou Yin

发明人： Joel Desouza ,  Devendra Sadana ,  Katherine Saenger ,  Chun-yung Sung ,  Min Yang ,  Haizhou Yin

IPC分类号： H01L27/12

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

摘要： Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

摘要翻译： 混合定向衬底允许制造互补金属氧化物半导体（CMOS）电路，其中n型场效应晶体管（nFET）以优选的电子迁移率的半导体取向设置，并且p型场效应晶体管（pFET） 以半导体方向设置，其对于空穴迁移率是最佳的。 本发明公开了完全形成在最佳半导体取向中的FET的性能优点可以通过仅需要将器件的沟道设置在具有最佳取向的半导体中来实现。 描述了各种新的FET结构，其特征在于，至少部分FET通道的FET的源极和/或漏极的至少一部分具有不同的取向。 可以并入其中可并入这些新的FET的混合基板及其制造方法。

公开(公告)号：US20060154429A1

公开(公告)日：2006-07-13

申请号：US11031142

申请日：2005-01-07

申请人： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

发明人： Joel de Souza ,  Keith Fogel ,  John Ott ,  Devendra Sadana ,  Katherine Saenger

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/2022

摘要： The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal. The invention also provides a low-defect density changed-orientation Si formed by ATR for use in hybrid orientation substrates.

摘要翻译： 本发明提供一种通过非晶化/模板化再结晶（ATR）工艺形成低缺陷密度变化取向Si的方法，其中具有第一晶体取向的Si区域通过离子注入而非晶化，然后再结晶成模板层的取向 具有不同的方向。 更一般地，本发明涉及消除由离子注入诱导的非晶化形成的含Si单晶半导体材料中剩余的缺陷所需的高温退火条件和从取向可以相同或不同的层的模板化再结晶 非晶层的原始方向。 本发明方法的关键组分是在1250-1330℃的温度范围内进行数分钟至数小时的热处理，以去除在初始再结晶退火之后残留的缺陷。 本发明还提供了一种用于混合取向基板的ATR形成的低缺陷密度变化取向Si。