公开(公告)号：US5978272A

公开(公告)日：1999-11-02

申请号：US871589

申请日：1997-06-06

申请人： Hao Fang ,  Sameer Haddad ,  Nader Radjy

发明人： Hao Fang ,  Sameer Haddad ,  Nader Radjy

IPC分类号： G11C16/04 ,  H01L29/423 ,  H01L29/788 ,  G11C11/34

CPC分类号： G11C16/0416 ,  H01L29/42324 ,  H01L29/7886 ,  G11C2216/10

摘要： A nonvolatile memory structure is disclosed. The nonvolatile memory structure includes a substrate, a heavily doped drain junction disposed in the substrate, and a lightly doped source junction disposed in the substrate. The source junction is diffused more deeply than the drain junction. The nonvolatile memory structure also includes a gate structure. The gate structure has a floating gate capacitively coupled to the substrate and a control gate capacitively coupled to the floating gate. The heavily doped drain junction has a central portion proximate to the gate structure. The lightly doped source junction also has a central portion proximate to the gate structure. At least the central portion of the lightly doped source junction is more lightly doped than the central portion of the heavily doped drain junction.

摘要翻译： 公开了非易失性存储器结构。 非易失性存储器结构包括衬底，设置在衬底中的重掺杂漏极结，以及设置在衬底中的轻掺杂源极结。 源极结比漏极结扩散更深。 非易失性存储器结构还包括栅极结构。 栅极结构具有电容耦合到衬底的浮动栅极和与浮动栅极电容耦合的控制栅极。 重掺杂漏极结具有靠近栅极结构的中心部分。 轻掺杂源极结还具有靠近栅极结构的中心部分。 至少轻掺杂源结的中心部分比重掺杂漏极结的中心部分更轻掺杂。

公开(公告)号：US5858844A

公开(公告)日：1999-01-12

申请号：US485871

申请日：1995-06-07

申请人： Hao Fang ,  Farrokh Omid-Zehoor ,  Todd Lukanc ,  Chris Schmidt

发明人： Hao Fang ,  Farrokh Omid-Zehoor ,  Todd Lukanc ,  Chris Schmidt

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28211 ,  H01L21/28114 ,  H01L29/42368 ,  H01L29/6659

摘要： The present invention comprises an innovative gate oxidation process after the disposition of the gate and prior to the disposition of the source and the drain by exposing the gate to oxygen at a predetermined temperature and for a predetermined time period for the optimized transistor performance. During the innovative gate oxidation process, oxygen penetrates into the interfaces of the gate conductive layer gate oxide and the gate dielectric layer silicon substrate and oxidizes portions of the gate conductive layer at the interfaces due to the oxygen smiling or the bird beak effect, which results in an increased effective thickness of the gate dielectric layer. Optionally, HCl can be introduced at a predetermined flowrate during the innovative gate oxidation process. A particular embodiment of the present invention is the fabrication of MOS transistors with polysilicon as the gate conductive layer and silicon oxide as the gate dielectric layer, and with the source and drain fabricated by the low doped drain (LDD) implant. In this particular case, the innovative gate oxidation process is a polysilicon oxidation (POX) process grown before LDD implant. The oxidation temperature and oxidation time duration for optimized transistor performances have been found to be 850.degree. C. and 115 minutes, respectively. This present invention is utilized to achieve maximum speed and performance by optimizing the POX process.

摘要翻译： 本发明包括在门的配置之后并且在通过在预定温度下将栅极暴露于氧气并在预定时间段内对于优化的晶体管性能进行设置之前的创新的栅极氧化工艺。 在创新的栅极氧化过程中，氧气渗透入栅极导电层栅极氧化物和栅极电介质层硅衬底的界面，并由于氧气微笑或鸟喙效应而在界面处氧化栅极导电层的部分，从而导致 在栅介电层的有效厚度增加。 任选地，可以在创新的栅极氧化过程期间以预定流量引入HCl。 本发明的一个具体实施例是制造具有多晶硅作为栅极导电层和氧化硅作为栅极介电层的MOS晶体管，并且通过低掺杂漏极（LDD）注入制造源极和漏极。 在这种特殊情况下，创新的栅极氧化工艺是在LDD植入之前生长的多晶硅氧化（POX）工艺。 已经发现优化的晶体管性能的氧化温度和氧化时间分别为850℃和115分钟。 本发明用于通过优化POX过程来实现最大速度和性能。

公开(公告)号：US5491657A

公开(公告)日：1996-02-13

申请号：US393636

申请日：1995-02-24

申请人： Sameer S. Haddad ,  Hao Fang

发明人： Sameer S. Haddad ,  Hao Fang

IPC分类号： G11C16/10 ,  G11C16/16 ,  G11C11/40

CPC分类号： G11C16/3477 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3486 ,  G11C2216/16 ,  G11C2216/18

摘要： There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.

摘要翻译： 提供了用于批量（或字节）编程闪存EEPROM存储器单元阵列的改进方法。 对阵列的衬底施加负电压。 将零编程的参考电压同时施加到要编程的所选存储单元的漏极区域。 同时也向所选择的存储器单元的控制栅极同时施加零伏特的相同参考电压。 本发明提供了仅需要单个低电压电源的存储单元的低电流消耗和快速编程。 耐久可靠性大于100,000次。

公开(公告)号：US5457336A

公开(公告)日：1995-10-10

申请号：US322811

申请日：1994-10-13

申请人： Hao Fang ,  Sameer Haddad ,  Chi Chang

发明人： Hao Fang ,  Sameer Haddad ,  Chi Chang

IPC分类号： H01L27/02 ,  H01L27/115

CPC分类号： H01L27/0251 ,  H01L27/115

摘要： An improved nonvolatile memory device is provided, in which the threshold voltage variations (V.sub.ts) and transconductance degradation are significantly reduced. The NVM includes protection structure for limiting the process induced damage incurred during the manufacturing process. The protection structure is utilized to provide reliable and stable dielectrical characteristics for the NVM device. The protection structure is easy to implement and will not affect the conventional NVM performance.

摘要翻译： 提供了一种改进的非易失性存储器件，其中阈值电压变化（Vts）和跨导劣化显着降低。 NVM包括用于限制在制造过程中产生的过程引起的损坏的保护结构。 该保护结构用于为NVM器件提供可靠和稳定的介电特性。 保护结构易于实现，不会影响传统的NVM性能。

公开(公告)号：US20150293697A1

公开(公告)日：2015-10-15

申请号：US14381879

申请日：2012-03-15

申请人： Hao Fang

发明人： Hao Fang

IPC分类号： G06F3/0489 ,  G06F3/0485 ,  G06F3/0484

CPC分类号： G06F3/04892 ,  G06F3/04842 ,  G06F3/0485 ,  G06F3/0489 ,  G06F16/954 ,  G06F16/957

摘要： A first web page referenced by a first resource locator is displayed in a user interface. The first web page includes second resource locators, each of which respectively references a corresponding second web page. A likelihood of selection of a particular second resource locator in the first web page is determined to be greater than respective likelihoods of selection of each of the remaining second resource locators in the first web page. A keyboard shortcut key is defined to the particular second resource locator such that a selection of the keyboard shortcut key results in a selection of the particular second resource locator. An indicator is displayed in the user interface indicating that the keyboard shortcut key is assigned to the particular second resource locator such that a request for the corresponding second web page is received in response to the selection of the keyboard shortcut key.

摘要翻译： 第一资源定位器引用的第一个网页显示在用户界面中。 第一网页包括第二资源定位符，每个资源定位器分别引用相应的第二网页。 确定在第一网页中选择特定的第二资源定位符的可能性被确定为大于在第一网页中选择每个剩余的第二资源定位符的各自的可能性。 键盘快捷键被定义到特定的第二资源定位符，使得键盘快捷键的选择导致特定的第二资源定位符的选择。 在用户界面中显示指示符，指示键盘快捷键被分配给特定的第二资源定位符，使得响应于键盘快捷键的选择接收对相应的第二网页的请求。

公开(公告)号：US20070274922A1

公开(公告)日：2007-11-29

申请号：US10570807

申请日：2004-09-07

申请人： Binghe Wang ,  Xingming Gao ,  Wenqian Yang ,  Hao Fang ,  Yun Yan

发明人： Binghe Wang ,  Xingming Gao ,  Wenqian Yang ,  Hao Fang ,  Yun Yan

IPC分类号： A61B5/00 ,  A61K31/47 ,  C07D215/02 ,  C07D215/12 ,  C12Q1/04 ,  G01N21/76

CPC分类号： C07F5/025 ,  G01N2021/6439

摘要： Described herein are boronic acid fluorescent compounds and methods of use thereof.

摘要翻译： 本文描述的是硼酸荧光化合物及其使用方法。

公开(公告)号：US07106536B2

公开(公告)日：2006-09-12

申请号：US10954599

申请日：2004-09-30

申请人： Hao Fang ,  Stephen Carl Kuehne

发明人： Hao Fang ,  Stephen Carl Kuehne

IPC分类号： G11B5/02

CPC分类号： H01F13/006 ,  G11B5/465

摘要： A demagnetizer for an inductive load having a driver circuit including at least one transistor and a ramp-down voltage source switchably connected to the driver circuit, so that when the ramp-down voltage source is connected to the transistor, it drives the voltage of the transistor below its threshold voltage.

摘要翻译： 一种用于感性负载的去磁器，具有包括至少一个晶体管的驱动器电路和可切换地连接到驱动器电路的斜降电压源，使得当斜坡下降电压源连接到晶体管时，其驱动电压 晶体管低于其阈值电压。

公开(公告)号：US06979619B1

公开(公告)日：2005-12-27

申请号：US09941370

申请日：2001-08-28

申请人： Hao Fang ,  Yue-Song He ,  Mark S. Chang ,  Kent K. Chang

发明人： Hao Fang ,  Yue-Song He ,  Mark S. Chang ,  Kent K. Chang

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11543

摘要： In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area. Finally, a nitridation process is provided in both the core and periphery areas subsequent to the previous steps. In a second aspect of the present invention, a flash memory device is disclosed. The flash memory device comprises core area having a plurality of memory transistors comprising an oxide layer, a first poly layer, an interpoly dielectric layer, and a second poly layer. The flash memory device further comprises a periphery area having a plurality of transistors comprising an oxide layer, a portion of the first poly layer, and the second poly layer. According to the present invention, the method for fabricating the flash memory device is a simplified process that results in a significant improvement in the oxide reliability in the core and periphery areas and also eliminates the nitrogen contamination problem in the periphery area.

摘要翻译： 在本发明的第一方面中，公开了一种制造闪速存储器件的方法。 该方法包括以下步骤：在存储器件的外围区域中提供双栅极氧化物的一部分，然后在存储器件的核心区域中同时提供双栅极氧化物，并在周边区域中完成双栅极氧化物。 最后，在上述步骤之后，在核心区域和外围区域都提供氮化处理。 在本发明的第二方面，公开了一种闪速存储器件。 闪存器件包括具有包括氧化物层，第一多晶硅层，多晶硅间介电层和第二多晶硅层的多个存储晶体管的核心区域。 闪存器件还包括具有包括氧化物层，第一多晶硅层的一部分和第二多晶硅层的多个晶体管的外围区域。 根据本发明，用于制造闪速存储器件的方法是简化的工艺，其显着提高了芯部和外围区域中的氧化物可靠性，并且还消除了周边区域中的氮污染问题。

公开(公告)号：US20050085046A1

公开(公告)日：2005-04-21

申请号：US10967198

申请日：2004-10-19

申请人： Jung-Cheng Kao ,  Hao Fang

发明人： Jung-Cheng Kao ,  Hao Fang

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/06

CPC分类号： H01L28/60 ,  H01L27/0629

摘要： A method of forming poly insulator poly capacitors by using self-aligned salicide process for mixed mode analog devices. These capacitors are formed in the self-aligned salicide process by stacked poly insulator poly (PIP). In the self-aligned salicide process, a self-aligned salicide block process is needed for preventing the salicide formation from electrostatic discharge (ESD) devices, resistors, or capacitors. The present invention uses the oxide layer of the self-aligned salicide block for the dielectric layer of the capacitors to form the PIP capacitor. Therefore, some process steps are omitted due to the formation of the PIP capacitors.

摘要翻译： 通过对混合模式模拟装置使用自对准自对准硅化物工艺形成多晶硅绝缘体多晶硅电容器的方法。 这些电容器通过堆叠的多晶硅绝缘体聚（PIP）在自对准的自对准硅化物工艺中形成。 在自对准的自对准硅化物工艺中，需要自对准的自对准硅化物阻挡工艺来防止由静电放电（ESD）器件，电阻器或电容器形成的自杀化合物。 本发明使用自对准硅化物块的氧化物层用于电容器的电介质层以形成PIP电容器。 因此，由于形成PIP电容器，省略了一些处理步骤。

公开(公告)号：US06815292B1

公开(公告)日：2004-11-09

申请号：US10260061

申请日：2002-09-27

申请人： Hao Fang ,  Mark S. Chang

发明人： Hao Fang ,  Mark S. Chang

IPC分类号： H01L2972

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531

摘要： A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.