公开(公告)号：US20100207251A1

公开(公告)日：2010-08-19

申请号：US12619464

申请日：2009-11-16

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Ming-Yen Chiu

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Ming-Yen Chiu

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： H01L21/78

摘要： A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a series of alternating dummy lines that are connected through dummy vias. The dummy lines are offset from dummy lines in adjacent metal layers. Additionally, the dummy lines and dummy vias in the upper layers of the scribe line may be formed with larger dimensions than the dummy lines and dummy vias located in the lower layers.

摘要翻译： 提出了一种在分割过程中防止违约的系统和方法。 一个实施例包括位于划线区域中的虚拟金属结构。 虚拟金属结构包括通过虚拟通孔连接的一系列交替虚拟线。 伪线与相邻金属层中的虚拟线偏移。 此外，划线的上层中的虚线和虚拟通路可以形成为具有比位于下层中的虚拟线和虚拟通孔更大的尺寸。

公开(公告)号：US20100194501A1

公开(公告)日：2010-08-05

申请号：US12759836

申请日：2010-04-14

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

IPC分类号： H01P3/08

CPC分类号： H01P3/08

摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.

摘要翻译： 公开了一种包括信号线和接地线的半导体器件。 信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

公开(公告)号：US07714443B2

公开(公告)日：2010-05-11

申请号：US11458501

申请日：2006-07-19

申请人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/52

CPC分类号： H01L21/76895 ,  H01L22/34 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/30105

摘要： An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.

摘要翻译： 互连结构至少包括第一互连层和第二互连层。 第一和第二互连层中的每一个具有焊盘结构，并且每个焊盘结构具有相应的焊盘密度。 第二互连层的焊盘结构的焊盘密度不同于第一互连层的焊盘结构的焊盘密度。 第一和第二互连层的焊盘结构彼此连接。

公开(公告)号：US07705696B2

公开(公告)日：2010-04-27

申请号：US11688903

申请日：2007-03-21

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

IPC分类号： H01P3/08

CPC分类号： H01P3/08

摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.

摘要翻译： 公开了一种包括信号线和接地线的半导体器件。 信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

公开(公告)号：US20090194889A1

公开(公告)日：2009-08-06

申请号：US12026312

申请日：2008-02-05

申请人： Shin-Puu Jeng ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen

发明人： Shin-Puu Jeng ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen

IPC分类号： H01L23/485

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/00

摘要： A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. In an embodiment, the conductive density of the connective layer is between approximately 20% and 100%.

摘要翻译： 提供了一种焊盘结构，其包括两个导电层和插入两个导电层的连接层。 连接层包括连续的导电结构。 在一个实施例中，邻接的导电结构是导电材料的固体层。 在其它实施例中，连续导电结构是包括例如矩阵配置或多个导电条纹的导电网络。 至少一个电介质间隔物可以插入导电网络。 在一个实施例中，连接层的导电密度在大约20％和100％之间。

公开(公告)号：US20090140393A1

公开(公告)日：2009-06-04

申请号：US12054082

申请日：2008-03-24

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Yu-Wen Liu

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Yu-Wen Liu

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer having a multi-layer wiring structure is disclosed. The wafer comprises a plurality of chip die areas arranged on the wafer in an array and scribe line areas between the chip die areas. The scribe lines of a semiconductor wafer having USG top-level wiring layers above ELK wiring layers have at least one metal film structures substantially covering corner regions where two scribe lines intersect to inhibit delamination at the USG/ELK interface during wafer dicing operation.

摘要翻译： 公开了具有多层布线结构的半导体晶片。 晶片包括排列在晶片上的多个芯片管芯区域和在芯片管芯区域之间的划线区域。 具有在ELK布线层之上的USG顶层布线层的半导体晶片的划线具有至少一个金属膜结构，其基本上覆盖两个划线相交的拐角区域，以在晶片切割操作期间在USG / ELK界面处抑制分层。

公开(公告)号：US07512924B2

公开(公告)日：2009-03-31

申请号：US11333618

申请日：2006-01-17

申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

IPC分类号： G06F17/50

CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

公开(公告)号：US07449785B2

公开(公告)日：2008-11-11

申请号：US11347378

申请日：2006-02-06

申请人： Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai

发明人： Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

摘要翻译： 提供半导体衬底上的焊料凸块。 焊料凸块包括其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的 邻近第一开口的顶部的部分。 所述焊料凸块还包括在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块 。

公开(公告)号：US20070182007A1

公开(公告)日：2007-08-09

申请号：US11347378

申请日：2006-02-06

申请人： Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai

发明人： Shin-Puu Jeng ,  Hao-Yi Tsai ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

摘要翻译： 提供半导体衬底上的焊料凸块。 焊料凸块包括其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的 邻近第一开口的顶部的部分。 所述焊料凸块还包括在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块 。

公开(公告)号：US20070015365A1

公开(公告)日：2007-01-18

申请号：US11181433

申请日：2005-07-14

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

IPC分类号： H01L21/461

CPC分类号： H01L21/3212 ,  H01L21/31053

摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.