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公开(公告)号：US10062693B2
公开(公告)日：2018-08-28
申请号：US15051790
申请日：2016-02-24
发明人： Takashi Ando , Martin M. Frank , Renee T. Mo , Vijay Narayanan , John Rozen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/823807 , H01L21/823857 , H01L21/8258 , H01L27/092
摘要： Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
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公开(公告)号：US20180197945A1
公开(公告)日：2018-07-12
申请号：US15801743
申请日：2017-11-02
发明人： Takashi Ando , Hemanth Jagannathan , Paul C. Jamison , John Rozen
CPC分类号： H01L28/75 , H01L21/02186 , H01L21/02244 , H01L21/02323
摘要： Methods of forming capacitors include forming a dielectric layer on a first metal layer. The dielectric layer is oxygenated such that interstitial oxygen is implanted in the dielectric layer. A second metal layer is formed on the dielectric layer. The dielectric layer is heated to release the interstitial oxygen and to oxidize the first and second metal layers at interfaces between the dielectric layer and the first and second metal layers.
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公开(公告)号：US20170243867A1
公开(公告)日：2017-08-24
申请号：US15051790
申请日：2016-02-24
发明人： Takashi Ando , Martin M. Frank , Renee T. Mo , Vijay Narayanan , John Rozen
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/823807 , H01L21/823857 , H01L21/8258 , H01L27/092
摘要： Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
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公开(公告)号：US09679967B1
公开(公告)日：2017-06-13
申请号：US15282152
申请日：2016-09-30
发明人： Takashi Ando , Kevin K. Chan , John Rozen , Jeng-Bang Yau , Yu Zhu
IPC分类号： H01L29/08 , H01L21/265 , H01L21/266 , H01L21/02 , H01L21/225 , H01L29/207
CPC分类号： H01L21/823418 , H01L21/02241 , H01L21/02546 , H01L21/0257 , H01L21/18 , H01L21/2233 , H01L21/2236 , H01L21/28575 , H01L21/3215 , H01L29/0847 , H01L29/20 , H01L29/452 , H01L29/66007 , H01L29/66522 , H01L29/6659 , H01L29/66628
摘要： A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.
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公开(公告)号：US09646886B1
公开(公告)日：2017-05-09
申请号：US14984471
申请日：2015-12-30
发明人： Vijay Narayanan , John Rozen
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/8234 , H01L29/51 , H01L21/28 , H01L21/02 , H01L27/088 , H01L29/20 , H01L29/49
CPC分类号： H01L21/28035 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/28079 , H01L21/28088 , H01L21/3003 , H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L21/8258 , H01L27/088 , H01L27/0886 , H01L29/20 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518
摘要： Disclosed is a process of making field-effect transistor gate stacks containing different deposited thin film silicon material layers having different hydrogen content, and devices comprising these gate stacks. The threshold voltage (Vt) can be tuned by tailoring the hydrogen content of the thin film silicon material layer positioned below a core dielectric and directly on a semiconductor material substrate.
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公开(公告)号：US20170092501A1
公开(公告)日：2017-03-30
申请号：US14962093
申请日：2015-12-08
发明人： Takashi Ando , Martin M. Frank , Vijay Narayanan , John Rozen
CPC分类号： H01L29/401 , H01L21/02181 , H01L21/0228 , H01L21/02304 , H01L21/28158 , H01L21/32105 , H01L29/4908 , H01L29/513 , H01L29/66757 , H01L29/66795
摘要： A method for forming a layer of material on a silicon layer comprises depositing a layer of silicon material having a hydrophobic H-terminated surface on a substrate, forming a hydrophilic seed layer on the surface of the silicon material, and depositing an oxide material layer on the hydrophilic seed layer.
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公开(公告)号：US11455521B2
公开(公告)日：2022-09-27
申请号：US16290585
申请日：2019-03-01
发明人： Teodor K. Todorov , Douglas M. Bishop , Jianshi Tang , John Rozen
摘要： A neuromorphic semiconductor device includes a copper-based intercalation channel disposed on an insulative layer, a source contact and a drain contact of a substrate. A copper-based electrolyte layer is disposed on the copper-based intercalation channel and a copper-based gate electrode is disposed on the copper-based electrolyte layer.
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公开(公告)号：US20210151669A1
公开(公告)日：2021-05-20
申请号：US17132703
申请日：2020-12-23
发明人： Teodor K. Todorov , Douglas M. Bishop , Jianshi Tang , John Rozen
摘要： Methods of forming variable-resistance devices include forming a variable-resistance layer between a first terminal and a second terminal from a material that varies in resistance based on an oxygen concentration. An electrolyte layer is formed over the variable-resistance layer from a material that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. A conductive gate layer is formed over the electrolyte layer.
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公开(公告)号：US10957937B2
公开(公告)日：2021-03-23
申请号：US16295986
申请日：2019-03-07
发明人： Teodor K. Todorov , Takashi Ando , Vijay Narayanan , John Rozen
IPC分类号： H01M10/0562 , H01G11/56 , H01L45/00 , H01M4/58 , H01M10/0525
摘要： Three-terminal solid state Cu-ion actuated analog switching devices are provided. In one aspect, a method of forming a switching device includes: depositing a channel layer on a substrate; forming a source contact and a drain contact on opposite ends of the channel layer; forming a solid electrolyte on the channel layer over the source contact and the drain contact; and depositing a gate onto the solid electrolyte, wherein the source contact, the drain contact, and the gate are three terminals of the switching device. A switching device and a method of operating a switching device are also provided.
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公开(公告)号：US10886467B2
公开(公告)日：2021-01-05
申请号：US16401693
申请日：2019-05-02
发明人： Hiroyuki Miyazoe , Qing Cao , Takashi Ando , John Rozen
摘要： A method is presented for constructing conductive bridging random access memory (CBRAM) stacks. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a CBRAM stack including at least an electrolyte layer, a conductive layer, a metal cap layer, and a top electrode such that a top end of the CBRAM stack has a smaller critical dimension than a bottom end of the CBRAM stack, forming a low-k dielectric layer over the CBRAM stack, and exposing a top surface of the CBRAM stack during a via opening.
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