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公开(公告)号:US10763340B2
公开(公告)日:2020-09-01
申请号:US16129329
申请日:2018-09-12
发明人: Sanghoon Lee , Effendi Leobandung , Renee Mo , Brent A. Wacaser
IPC分类号: H01L29/66 , H01L29/06 , H01L29/786 , H01L29/04 , H01L29/423 , H01L29/20 , B82Y10/00 , H01L29/775 , H01L29/78 , H01L29/08 , H01L21/762 , H01L21/306 , H01L21/308 , H01L21/02 , H01L21/265 , H01L21/8258
摘要: In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.
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52.
公开(公告)号:US10755925B2
公开(公告)日:2020-08-25
申请号:US16516835
申请日:2019-07-19
发明人: Stephen W. Bedell , Cheng-Wei Cheng , Kunal Mukherjee , John A. Ott , Devendra K. Sadana , Brent A. Wacaser
IPC分类号: H01L21/02 , H01L21/3065 , H01L21/306 , H01L29/04
摘要: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
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53.
公开(公告)号:US20200027690A1
公开(公告)日:2020-01-23
申请号:US16039855
申请日:2018-07-19
IPC分类号: H01J37/147 , G01N23/207
摘要: Techniques for high throughput electron channeling contrast imaging (ECCI) by varying electron beam energy are provided. In one aspect, a method for ECCI of a crystalline wafer includes: placing the crystalline wafer under an electron microscope having an angle of less than 90° relative to a surface of the crystalline wafer; generating an electron beam, by the electron microscope, incident on the crystalline wafer; varying an accelerating voltage of the electron microscope to access a channeling condition of the crystalline wafer; and obtaining an image of the crystalline wafer. A system for ECCI is also provided.
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54.
公开(公告)号:US20190341250A1
公开(公告)日:2019-11-07
申请号:US16516835
申请日:2019-07-19
发明人: Stephen W. Bedell , Cheng-Wei Cheng , Kunal Mukherjee , John A. Ott , Devendra K. Sadana , Brent A. Wacaser
IPC分类号: H01L21/02 , H01L21/306 , H01L21/3065 , H01L29/04
摘要: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
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公开(公告)号:US20190318193A1
公开(公告)日:2019-10-17
申请号:US16455141
申请日:2019-06-27
摘要: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.
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公开(公告)号:US10319838B2
公开(公告)日:2019-06-11
申请号:US14876986
申请日:2015-10-07
摘要: A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a sidewall of the structure defined by the silicon material; adjusting a growth condition to facilitate a first growth rate of the III-V material in directions along a surface of the sidewall and a second growth rate of the III-V material in a direction laterally from the surface of the sidewall, wherein the second growth rate is less than the first growth rate; and processing the silicon material and the III-V material to form a fin.
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公开(公告)号:US10043663B2
公开(公告)日:2018-08-07
申请号:US15395805
申请日:2016-12-30
IPC分类号: H01L29/00 , H01L21/02 , C30B23/02 , C30B25/18 , C30B25/04 , C30B23/04 , C30B29/40 , C30B29/52 , H01L29/66 , H01L29/04
摘要: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.
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公开(公告)号:US20180211376A1
公开(公告)日:2018-07-26
申请号:US15413532
申请日:2017-01-24
CPC分类号: G06T7/0004 , G06K9/00134 , G06T11/60 , G06T2207/10056 , G06T2207/30148 , H01J37/222 , H01J37/292
摘要: A method for crystal analysis includes identifying a crystalline region on a device where an electronic channeling pattern is needed to be determined, acquiring a whole image for each of a plurality of different positions for the crystalline region using a scanning electron microscope (SEM) as the crystalline region is moved to different positions. Relevant regions are extracted from the whole images. The images of the relevant regions are stitched together to form a composite map of a full electron channeling pattern representative of the crystalline region wherein the electronic channeling pattern is provided due to an increase in effective angular range between a SEM beam and a surface of the crystal region.
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公开(公告)号:US20180145154A1
公开(公告)日:2018-05-24
申请号:US15874208
申请日:2018-01-18
CPC分类号: H01L29/66795 , H01L21/02422 , H01L21/0245 , H01L21/02538 , H01L21/0254 , H01L21/02587 , H01L29/1054 , H01L29/785
摘要: A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a sidewall of the structure defined by the silicon material; adjusting a growth condition to facilitate a first growth rate of the III-V material in directions along a surface of the sidewall and a second growth rate of the III-V material in a direction laterally from the surface of the sidewall, wherein the second growth rate is less than the first growth rate; and processing the silicon material and the III-V material to form a fin.
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公开(公告)号:US09905637B2
公开(公告)日:2018-02-27
申请号:US15135148
申请日:2016-04-21
IPC分类号: H01L33/00 , H01L29/06 , H01L29/78 , H01L29/66 , H01L29/201 , H01L29/267 , H01L29/08 , H01L29/10 , H01L29/207 , H01L29/24 , H01L29/26 , H01L29/861 , H01L29/22
CPC分类号: H01L29/267 , H01L29/0607 , H01L29/0634 , H01L29/0843 , H01L29/0847 , H01L29/1054 , H01L29/20 , H01L29/201 , H01L29/207 , H01L29/2206 , H01L29/227 , H01L29/24 , H01L29/263 , H01L29/66204 , H01L29/66219 , H01L29/66522 , H01L29/66969 , H01L29/78 , H01L29/7848 , H01L29/7849 , H01L29/861 , H01L29/8613
摘要: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm−2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.
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