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公开(公告)号：US11411160B2
公开(公告)日：2022-08-09
申请号：US16748277
申请日：2020-01-21
摘要： Techniques regarding qubit devices comprising silicon-based Josephson junctions and/or the manufacturing of qubit devices comprising silicon-based Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes.
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2.发明授权公开(公告)号：US10714303B2
公开(公告)日：2020-07-14
申请号：US16039855
申请日：2018-07-19
IPC分类号： H01J37/00 , H01J37/147 , G01N23/207
摘要： Techniques for high throughput electron channeling contrast imaging (ECCI) by varying electron beam energy are provided. In one aspect, a method for ECCI of a crystalline wafer includes: placing the crystalline wafer under an electron microscope having an angle of less than 90° relative to a surface of the crystalline wafer; generating an electron beam, by the electron microscope, incident on the crystalline wafer; varying an accelerating voltage of the electron microscope to access a channeling condition of the crystalline wafer; and obtaining an image of the crystalline wafer. A system for ECCI is also provided.
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公开(公告)号：US10157993B2
公开(公告)日：2018-12-18
申请号：US15183336
申请日：2016-06-15
IPC分类号： H01L29/66 , H01L21/265 , H01L21/28 , H01L29/08 , H01L29/267 , H01L29/43
摘要： A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type layer includes ZnO. An aluminum contact is formed in direct contact with the ZnO of the n-type material to form an electronic device.
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4.发明申请公开(公告)号：US20180277367A1
公开(公告)日：2018-09-27
申请号：US15467265
申请日：2017-03-23
发明人： Stephen W. Bedell , Cheng-Wei Cheng , Kunal Mukherjee , John A. Ott , Devendra K. Sadana , Brent A. Wacaser
IPC分类号： H01L21/02 , H01L29/04 , H01L21/306 , H01L21/3065
CPC分类号： H01L21/02694 , H01L21/02488 , H01L21/02513 , H01L21/02538 , H01L21/02546 , H01L21/02609 , H01L21/02614 , H01L21/02664 , H01L21/02667 , H01L21/30617 , H01L21/3065 , H01L29/04
摘要： A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
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公开(公告)号：US10038057B2
公开(公告)日：2018-07-31
申请号：US15450649
申请日：2017-03-06
IPC分类号： H01L29/68 , H01L29/43 , H01L29/08 , H01L29/267 , H01L29/78 , H01L29/66 , H01L29/868 , H01L29/861 , H01L29/06
CPC分类号： H01L29/0847 , H01L29/0649 , H01L29/0895 , H01L29/267 , H01L29/66219 , H01L29/66522 , H01L29/66613 , H01L29/66643 , H01L29/66969 , H01L29/78 , H01L29/861 , H01L29/868
摘要： A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.
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公开(公告)号：US09972688B2
公开(公告)日：2018-05-15
申请号：US15363625
申请日：2016-11-29
CPC分类号： H01L29/34 , H01L21/02381 , H01L21/0254 , H01L21/02543 , H01L21/02546 , H01L21/02664 , H01L21/3245 , H01L29/0603 , H01L29/20 , H01L29/2003
摘要： A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.
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公开(公告)号：US09859397B2
公开(公告)日：2018-01-02
申请号：US15585231
申请日：2017-05-03
发明人： Sanghoon Lee , Effendi Leobandung , Renee Mo , Brent A. Wacaser
IPC分类号： H01L29/06 , H01L29/66 , H01L21/265 , H01L29/786 , H01L29/04 , H01L29/423 , H01L21/762 , H01L21/306 , H01L21/308 , H01L29/20 , H01L21/02
CPC分类号： H01L29/66522 , B82Y10/00 , H01L21/02381 , H01L21/0242 , H01L21/02422 , H01L21/02433 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02538 , H01L21/02603 , H01L21/02639 , H01L21/02645 , H01L21/26546 , H01L21/30604 , H01L21/30608 , H01L21/30612 , H01L21/30617 , H01L21/3083 , H01L21/3086 , H01L21/7624 , H01L21/8258 , H01L29/045 , H01L29/0673 , H01L29/0847 , H01L29/20 , H01L29/42384 , H01L29/42392 , H01L29/66469 , H01L29/775 , H01L29/7853 , H01L29/78681 , H01L29/78696
摘要： In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.
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公开(公告)号：US09527107B2
公开(公告)日：2016-12-27
申请号：US13739663
申请日：2013-01-11
IPC分类号： B05C19/04 , B05D1/00 , C23C14/00 , C23C14/04 , C23C14/22 , C23C14/24 , C23C14/26 , C23C14/34 , C23C14/50 , C23C16/44 , C23C16/455 , C23C16/458 , F16C32/06 , C23C16/448
CPC分类号： B05D1/00 , B05C19/04 , C23C14/00 , C23C14/04 , C23C14/228 , C23C14/24 , C23C14/26 , C23C14/34 , C23C14/50 , C23C16/4481 , C23C16/45517 , C23C16/45563 , C23C16/45585 , C23C16/458 , C23C16/4583 , F16C32/0603
摘要： An apparatus for particle deposition is disclosed. The apparatus includes a housing configured to couple to a work piece to form a chamber. A nozzle directs a working gas into the chamber to deposit a particle entrained in the working gas at the work piece. The nozzle may be coupled to a flow channel within the chamber that directs the working gas through the nozzle. The coupling between the housing and the work piece may be a slidable coupling.
摘要翻译： 公开了一种用于颗粒沉积的装置。 该装置包括构造成联接到工件以形成腔室的壳体。 喷嘴将工作气体引导到室中以将夹带在工作气体中的颗粒沉积在工件上。 喷嘴可以联接到室内的流动通道，其引导工作气体通过喷嘴。 壳体和工件之间的联接可以是可滑动的联接件。
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公开(公告)号：US20160118248A1
公开(公告)日：2016-04-28
申请号：US14525594
申请日：2014-10-28
IPC分类号： H01L21/02 , H01L29/267
CPC分类号： H01L21/02488 , H01L21/02373 , H01L21/02538 , H01L21/02546 , H01L21/02614
摘要： A semiconductor structure can be created by forming an insulator layer over a surface of a substrate. An intermediate layer can be formed on top of the insulator layer, wherein openings in the intermediate layer may expose regions of the insulator. Openings may be formed in the exposed regions of the insulator layer to create exposed areas of the substrate. A first element of a multi-element semiconductor can be deposited onto the exposed regions of the insulator layer, into the openings in the exposed regions of the insulator layer, and onto the exposed areas of the substrate. A capping layer can be formed over the first element of the multi-element semiconductor. The first element can be melted. A liquid solution can be created by dissolving a second element of the multi-element semiconductor into first element. A multi-element semiconductor, seeded off the substrate, can be formed from the liquid solution.
摘要翻译： 可以通过在衬底的表面上形成绝缘体层来形成半导体结构。 可以在绝缘体层的顶部上形成中间层，其中中间层中的开口可以暴露绝缘体的区域。 可以在绝缘体层的暴露区域中形成开口，以形成衬底的暴露区域。 可以将多元素半导体的第一元素沉积到绝缘体层的暴露区域上，进入绝缘体层的暴露区域中的开口中以及衬底的暴露区域上。 可以在多元件半导体的第一元件上形成覆盖层。 第一个元素可以融化。 可以通过将多元素半导体的第二元素溶解在第一元素中来产生液体溶液。 可以从液体溶液形成从衬底上撒下的多元素半导体。
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公开(公告)号：US20150318352A1
公开(公告)日：2015-11-05
申请号：US14797945
申请日：2015-07-13
摘要： A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.
摘要翻译： 提供了一种在用于半导体器件应用的半导体衬底的表面上制造模板化半导体纳米线的方法。 该方法包括通过使用氧反应种子材料来控制半导体纳米线的空间位置。 本发明还提供包括半导体纳米线的半导体结构。 在又一个实施例中，提供了在随后的退火步骤期间能够与氧反应元件形成化合物半导体合金的化合物半导体衬底或其它类似衬底的图案化。 该实施例提供可用于各种应用的图案化衬底，包括例如半导体器件制造，光电器件制造和太阳能电池器件制造。
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